Hi,
I have a question regarding the ARM PLL configuration for keystone 2 devices. I have studied the source code for U-Boot from the arago-project and in clock.c (/arch/arm/cpu/armv7/keystone) I stumbled upon the following:
There seems to be a glitch free bypass enable bit located in the CHIPMISCCTL1 register which is only applicable for kepler. I haven't found any documentation mentioning this, so my question is: Can anyone tell me a bit more about this bit and what is meant with kepler?
Thanks!
Raymond
This is a repost. Original: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/260831.aspx