Other Parts Discussed in Thread: DM3730, TPS65950
Hi,
I work on DM3730 processor and DPLL clock settings for uart3 module. Some values about my boards are:
OSC_SYS_CLK = 26 MHz
SYS_CLK = OSC_SYS_CLK / 2 = 13 MHz
According to Figure 3-61. Common CM Source-Clock Controls on DM3730 Technical Referance Manual:
Setup CM_CLKSEL2_PLL, which sets up M and N for DPLL4. = M = 576, N = 6
Setup CM_CLKSEL3_PLL, which sets up M2 for DPLL4 = M2 = 13
So my PER_48M_FCLK is 48 MHz. Then with "Baud rate = (functional clock/16)/N" formula, my divisor value is 26 for 115200 baudrate. But this setup only works 57600 baud rate with upper PLL settings.
Aslo my other question: I use external oscillator (TPS65950) with 26 MHz and selected sys_boot[6] is 1(for using of an external square clock source). It doesn't work correctly(upper problem occurs). Then I selected sys_boot[6] is 0. But it also doesn't work correctly. Moreover, these 2 setup configurations show same behavior(57600 baud problem).
What do you think about my problems?
Regards,
Emre
