I'm currently working out a scheme for low power mode operation for a product using the OMAP L138. The note below is from a footnote below table 8-1 in section 8.2.1 of the OMAP L138 TRM.
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
Which domains need to maintain the 1:2:4 ratios? The two clocks that are configured to maintain this ratio by default (SYSCLK2 and SYSCLK4) have a fixed clock ratio. What specifically does this statement refer to?