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Lowering clock speed for power savings on the OMAP L138

Other Parts Discussed in Thread: OMAPL138

I'm currently working out a scheme for low power mode operation for a product using the OMAP L138.  The note below is from a footnote below table 8-1 in section 8.2.1 of the OMAP L138 TRM.   

The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.

Which domains need to maintain the 1:2:4 ratios?  The two clocks that are configured to maintain this ratio by default (SYSCLK2 and SYSCLK4) have a fixed clock ratio.  What specifically does this statement refer to?

  • Hi Dinesh,

    The relationship between the system clocks has been explained in the table 8-1 in the OMAPL138 Technical Reference manual. The table in the TRM should clarify the statement. Basically the dividers on SYSCLK3 , SYSCLK5 and SYSCLK7 have no restrictions on them except to follow the max and min frequencies specified in the spec.

    SYSCLK1 = SYSCLK6 (Always)

    SYSCLK1: SYSCLK2  = 1:2 ( maintain this fixed ratio) -> It means the divider values for obtaining the clock can be changed but the fixed clock ratio needs to be maintained.

    SYSCLK1: SYSCLK4 =1:4 ( maintain this fixed ratio) -> It means the divider values for obtaining the clock can be changed but the fixed clock ratio needs to be maintained.

    In addition to the technical reference manual, we provide a clocking spreadsheet that can be found here:

    http://processors.wiki.ti.com/index.php/Programming_PLL_Controllers_on_OMAP-L1x8/C674x/AM18xx

    This should help you configure your system clock and find the values of the dividers required to obtain that configuration.

    Regards,

    Rahul

  • Hi Rahul,

    Thanks for the explanation.  I haven't got around to writing any code to test this out but this explanation is more thorough than the one in the datasheet.  I'll set this as verified. Apologies for the delay.

    Regards,

    Dinesh