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BAR0 not visible from RC

aymeric dupont
Expert 1200 points

Dear support,

I hope you can help me with this very strange issue that we are experiencing. I am not sure if I should classify my problemas a Boot Issue or Pcie Issue.

The RBL enables the C6670 to boot from PCIe. However, the default window size are too big for our host to allocate memory and access all the bars.

Because of this problem, we created our own IBL based on the code provided by TI in the function iblPCIeWorkaround from mcsdk_2_01_00_03\tools\boot_loader\ibl\src\device\c66x\.

For the last 2 month, we have been using successfully a bootstrap that starts the RBL in from SPI in CS1, retreives our IBL from flash memory, runs the IBL and we can see our board on the pcie bus with 5 bars from a linux host. (if you need I can provide the detail lspci command)
When looking at this command we can identify 5 BARS that are configured as our IBL set them up.


BAR0: 32k
BAR1,2,3: 1M
BAR4: 4M


We are updating our boot process to boot from EEPROM. We changed the boot strap. Since it is the same code, we just regenerated the binary file (updating the parameter passed to romparse.exe) and we store it in EEPROM. We did not change one line of the source code of our working IBL

For the last week we have beleived that the board was booting properly as we did not really need to do any memory/register access via the host. Moreover, the linux host sees the board (lspci) and updates the BAR registers (0x21800000+0x1010) on the EP.

However, we started to have strange issues reading and writing memory regions on the DSP from the host.
We we looked a bit further, lspci -x -v here was our surprise:
BAR1,2,3: 1M
BAR4: 4M


BAR0 has disapeared. According to you manual, BAR0 is the only bar that can be used to access the pcie registers. We spent a lot of time investigating and we narrow it down to:

Once the RBL boots from flash => all is good

Once the RBL boots from EEPROM (same problem for eeprom @0x50 or eeprom @0x51) => Not good

I can provide you the source code of the IBL under NDA if you need but perhpas you have an idea of what is going on or perhpas you have heard of such a problem.

Is there additional settings required in the IBL when booting from i2c that I do not require when I boot from SPI


Thanks in advance

Aymeric

  • 0
    TI__Genius 9915 points

    Aymeric,

    This is really strange. Does your BAR1,2 and 3 works fine in this case. I suspect that we are not loading the full image into the EEPROM flash. Did you checked the I2C boot itself. Like using the default IBL and see if that works?

    thanks,

    arun.

  • 0 in reply to ArunMani
    Expert 2145 points

    Hi Arun - you ask about checking the I2C boot.We have tried two different images in the EEPROM flash and the problem happens with both. One of the executables which we loaded into the EEPROM can be seen to be running correctly when the board powers up because it runs in a loop which checks the BAR register values and logs them to a serial terminal through the UART and toggles an LED. This loop is running as expected so I assume that means that the full image did get loaded into the EEPROM.

    Does that answer your question?

    Regards,
    Geraldine

  • 0
    TI__Guru* 95265 points

    Aymeric,

    Can you show me the lspci results for both cases? and what are the BAR registers (starting from 0x21801010 in DSP) for both cases? Did you tried to access EP's PCIE registers from Linux host in the failure case? For other DSP memories mapped by BAR1, 2, 3, ..4, can they be accessed from Linux? what happened?

    Regards, Eric

  • 0 in reply to Geraldine Maclear
    TI__Genius 9915 points

    Geraldine,

    Are you saying that both the images have the same problem? I am sorry, it was not really clear from your reply. if it is, then we might need to inspect the way you produce the image.

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    Expert 2145 points

    Eric, Arun - thanks for your replies.

    6378.PcieIssueData.zip

    I am attaching file PcieIssueData.zip.

    The zip file shows how the EEPROM image is produced and gives output from running the two test cases.

    All the .txt files contain results from running the two different cases. The cases are "EEPROM" and "SPI".

    BARreg_Xmc8320Boot : this file shows the memory browser contents from CCS after connecting to DSP_0 then DSP_1 and looking at the address 0x21801010.

    dmesg_Xmc8320Boot : this file contains the output after running "dmesg" on the Linux PC.

    pcix _Xmc8320Boot : this file contains the output after running "lspci -x -vv -d 104c:b004" on the Linux PC (Note: that is -v v, not -w in the arguments)

    run_script.bat shows how the .bin file gets created which is loaded into the EEPROM. It uses the files boot_script.rmd and eeprom_0.map and eeprom_1.map.

    Thanks,
    Geraldine

  • 0 in reply to Geraldine Maclear
    TI__Guru* 95265 points

    Geraldine,

    Thanks for providing the log. The failure case (EEPROM) BAR0 field is zero in DSP PCIE memory. The other BARs looks fine. Can Linux machine access the DSP memory mapped by those BARs?

    After processing the .OUT file by the run_script, the binary file wrote to EEPROM should be very small. What is the actual file size in bytes? In the past we met an issue, if the IBL file (we shrunk it for other purposes) is too small (~5KB vs the original ~50KB), the PCIE enumeration failed with certain ATX PC. It looks when the IBL code is smaller, it takes less time to load into DSP memory via I2C bus, so it starts to execute earlier when powered the on (the power is supplied by ATX PC). We added some delay in the code to solve the issue. I am not sure if BAR0 gone is related to this or not, but this is something we can try this if it helps?

    The way we did was:

    main() {

    added some cycles_delay at the beginning;

    then the code for PCIE workaround as in the IBL code; this is to delay the starting of PCIE configurtaion and link training

    } 

    The delay used is about 0.5 seconds from some trials. Then we built the code, convert and burnt it to EEPROM and worked. Perhaps you can try a few different values or on different PCs.

    Regards, Eric

     

  • 0 in reply to lding
    Expert 1200 points

    Hi Eric,

    Please find the result (same format as previous email).

    8322.PcieIssueDataWithHalfSecondDelay.zip

    The code written in the EEPROM is 63432 bytes which is fitting properly in the EEPROM. Therefore over I2C working 200kHz it is taking a long time to load. Nonetheless, we tried to add some delays that did not make any difference. For info, booting from SPI will take 110 time less time (clock set up at 20MHz and we do not experience this issue)

    Now it is bit difficult to tell you if linux can make use of these other bars because we have to set up the inbound translation which we usually do from the host. Since we cannot access the PCIe registers (BAR0) we cannot set up the inbound translation to access the DSP memory. We could default all the inbound registers to access the DDR at boot time when the RC writes the BAR addresses to the configuration register but I am not sure it would help us progress in the matter...

    I hope you have other ideas that could help us progress because we run out. I could provide the source code of the bootloader if you wish..

    Aymeric

  • 0 in reply to aymeric dupont
    TI__Guru* 95265 points

    Aymeric,

    The board you used is your customerized board with 2 6670 DSP on it, or 2 TI 6670 EVM cards in the Linux chassis? In the good case, what is the format for the program on SPI, is the same as in I2C (so the same binary file) or SPI file format are different? In the failure case, did PCIE debug0 register (0x21801728) show link up (L0 state)? 

    Regards, Eric

     

  • 0 in reply to lding
    Expert 1200 points

    Eric,

    For the info, Geraldine and I are working together on the problem this is why you are receiving emails from both of us.

    Yes, the board we are using is the customized board with 2 C6670 on it. Each DSP can access a flash memory (SPI interface) and an EPROM (I2c).

    DSP0 accesses his EEPROM @0x50 and DSP1 accesses his EEPROM @0x51.

    The boot strap is controlled by a CPLD. Therefore, if we boot from SPI, the same DEVSTAT is found on each DSP (). If we boot from EPROM, the only difference in the devstat is bit 11 (bit 10 of the bootmode). DEVSTAT DSP0: 0x3200B - DEVSTAT DSP1:0x3280B

    (for the background) Back in January, we spent a lot of time working with Arun regarding an issue with the bootloading from SPI. We found a bug in romparse.exe that crashing the DSP at boot. But since we resolved this issue, everything has gone very smoothly and we released our first bootimage.

    As you probably know, generating the image in EPROM or in FLASh must go through different utilities (especially the script that is parsed by romparse.exe). Therefore I cannot say that it is the same binary (I can provide them to you). It is the same coff file (CCS build) but it is them parsed differently.

    I am not sure I understand what you mean by "what is the format of the file", but I believe the "format" at the end is "the same" as it is a swapped version (this what Arun said we need to use the utilities from TI). Geraldine provided you with the script we are using to generate the end format file.

    The EpromWriter and NorWriter were not touched. These are the one provided by TI apart that they are calling our platform library rather than TI platform library.

    Finally, in case of "~failure~", the value @0x21801728 is 0x0360 0911 where we have 0x11 for the LTSSM state which is ok.

    When booting from PCI, this is the value in the debug0 register 0x030A EA11 which is the same considering that (PIPE Transmit data. Reset value is zero but changes at every clock after that)

    Partial errors are tricky. Thanks so much for the help, anything I can provide, let me know.

  • 0 in reply to aymeric dupont
    Expert 2145 points

    Hi Eric and Arun - is there any update on this?

    Thanks,
    Geraldine

  • 0 in reply to Geraldine Maclear
    TI__Guru* 95265 points

    Geraldine,

    I went through your PCIE portion code and didn't find problems. One thing I plan to do is to put your PCIE portion code into our IBL and flash to EEPROM to see if I can reproduce the issue or not.

    I am not sure if you have 6670 or 6678 EVM card at your end and had did this test already. Please let me know.

    Also, for the conversion from the .out file to .bin file file in EEPROM, can you send me the whole toolset you used so I can use the same?

    Regards, Eric 

  • 0 in reply to lding
    Expert 2145 points

    Hi Eric - thanks for your reply. I'm sending a partial response now containing the whole toolset.

    It contains the following files which are used in run_script.bat:

    c:\TI_CCS\ccsv5\tools\compiler\c6000_7.4.1\bin\hex6x

    C:\spectrum\components\xmc8320\third_party\TI_BIN_UTILITIES\b2i2c.exe

    C:\spectrum\components\xmc8320\third_party\TI_BIN_UTILITIES\b2ccs

    C:\spectrum\components\xmc8320\third_party\TI_BIN_UTILITIES\romparse_fix_prediv.exe

    C:\spectrum\components\xmc8320\third_party\TI_BIN_UTILITIES\byteswapccs

    C:\spectrum\components\xmc8320\third_party\TI_BIN_UTILITIES\ccs2bin  

    Thanks,
    Geraldine

    1854.PcieIssueToolSet.zip

  • 0 in reply to Geraldine Maclear
    TI__Guru* 95265 points

    Geraldine,

    I was able to reproduce your issue after placing your PCIE code into our IBL and writing to EEPROM, I am debugging it. As you mentioned that SPI boot is fine in your case for the exact code, do you use NAND or NOR? Assuming you have a .out file built by TI cgtools, then what conversion steps used and what the final files flashed to (NAND/NOR) in SPI boot?

    Regards, Eric 

  • 0 in reply to lding
    Expert 1200 points

    Hello Eric,

    I never thought I would be so happy to know that you can reproduce our problem. At least we can focus on a SW issue rather than HW, or timing or host, this is a big move forward on our side. We can now focus on the SW on the C6670.

    For the SPI boot, we are using a Nor Flash on CS1. If Arun provided you the source code Xmc8320BootImage.zip, you will see that in CCS create the .out in a bin directory. Inside the bin directory, there are 2 directories that enable the creation of the binary file either for a SPI peripheral or an i2c peripheral.

    Going through any of these directories, you will find a batch file run_script.bat which calls all the necessary TI utilities to go from an out file to a bin file with the boot table in front of the "real code".

    The only difference between your utilities and the one we are using is that we had to fix a bug inside the romparse.exe utility (line 508 of romparse.c, current_table.common.swPllCfg_lsw |= ((value & 0xff) << 16); should have been current_table.common.swPllCfg_lsw |= ((value & 0xff) << 8);) which cause the C6670 to boot overclocked...

    For both peripherals, spi.map, eeprom_0.map and eeprom_1.map are the set of parameters we are providing romparse to generate the boot table. If you have any question regarding these parameters, let me know.

    Aymeric

  • 0 in reply to aymeric dupont
    TI__Guru* 95265 points

    Aymeric,

    I thought the conversion steps and utilities used for SPI boot and I2C boot are the same, only the difference is the .map used for romparse. And SPI boot always works, right?

    Some update from my side, I tried different BAR settings with your code and I still get BAR0 missing. On our IBL code, I tried your BAR set up and I can get all BARs correct:

     if (flag_6678)  {
      /* 6678 */
      DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0x00007FFF);   /* 64K */
      DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR1), 0x000FFFFF);   /* 1M */
      DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR2), 0x000FFFFF);   /* 1M */
      DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR3), 0x000FFFFF);   /* 1M */
      DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR4), 0x003FFFFF);   /* 4M */
      DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR5), 0x00000000);   /* 0 */
     }

    04:00.0 Multimedia controller: Texas Instruments Device b005 (rev 01)
            Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
            Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
            Latency: 0, Cache Line Size: 64 bytes
            Interrupt: pin A routed to IRQ 11
            Region 0: Memory at f7b00000 (32-bit, non-prefetchable) [size=1M]
            Region 1: Memory at f7600000 (32-bit, prefetchable) [size=1M]
            Region 2: Memory at f7500000 (32-bit, prefetchable) [size=1M]
            Region 3: Memory at f7400000 (32-bit, prefetchable) [size=1M]
            Region 4: Memory at f7000000 (32-bit, prefetchable) [size=4M]
            Capabilities: <access denied>

    I are still debugging what difference caused this.

    Regards, Eric

     

  • 0 in reply to lding
    Expert 1200 points

    Hi Eric,

    Thanks for the feedback. You are correct, the steps and the utilities for the SPI and the I2C are identical, the only difference is the map file that is provided to the romparse utility. SPI always works, I have been using this spi boot image for the last three month.

    I just want to confirm one think. When you say you are running our code, does that mean that you substituted the funcion iblPCIeWorkaround (original TI code) with PCIE_INIT_InitPeripheral (our code)? By doing that, the BAR0 disappears?

    Aymeric

  • 0 in reply to aymeric dupont
    TI__Guru* 95265 points

    Aymeric,

    "I just want to confirm one think. When you say you are running our code, does that mean that you substituted the funcion iblPCIeWorkaround (original TI code) with PCIE_INIT_InitPeripheral (our code)? By doing that, the BAR0 disappears?"

    Yes, this is what I did. At the beginning I also added code to turn PCIE on via PSC.

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    Aymeric,

    After many trials, please make the following changes in your code:

    1) PCIE_LINK_STAT_CTRL (0x21801080) bit 28, please set this to 1

    2) In your code there is function pcie_init_SetBarAddressRegisters(), please split this into 2 functions. The first function just clears the dbi_cs2. The second does the rest (set prefetch or not for BARs). Then call the function in the following orders:

       fun1();
       
       DEVICE_REG32_W (STATUS_CMD), );
       DEVICE_REG32_W (DEV_STAT_CTRL), );
       DEVICE_REG32_W (ACCR), ); 
       fun2();

    This verified both in my IBL with/without using your PCIE code on C6678 EVM. Can you please try on your board? Hope this resolve your issue.

    Regards, Eric 

  • 0 in reply to lding
    Expert 1200 points

    Hi Eric,

    For a while you gave us big hopes. I sent you the update to our code privately following your recommendations.

    The result is that it does not make any change. The situation is exactly the same as it was before.

    I sent you another file privately which is the revised version of c66xinit.c to run our initialization inside TI IBL.I just want to make sure we are on the same page.

    I have to say that the result are quite not what I was expecting. With our code, BAR0 is not available (we already knew that), but the windows are also  not the size I am setting them up.

    Fullscreen 5773.spectrumBars.txt Download 
    00:00.0 Host bridge: Intel Corporation 82X38/X48 Express DRAM Controller
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel driver in use: x38_edac
	Kernel modules: x38_edac
00: 86 80 e0 29 06 01 90 20 00 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:01.0 PCI bridge: Intel Corporation 82X38/X48 Express Host-Primary PCI Express Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: e8000000-eaffffff
	Prefetchable memory behind bridge: 00000000c0000000-00000000dfffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 e1 29 07 05 10 00 00 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 10 10 00 00
20: 00 e8 f0 ea 01 c0 f1 df 00 00 00 00 00 00 00 00
30: 00 00 00 00 88 00 00 00 00 00 00 00 0a 01 1a 00

00:06.0 PCI bridge: Intel Corporation 82X38/X48 Express Host-Secondary PCI Express Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=08, subordinate=08, sec-latency=0
	Prefetchable memory behind bridge: 00000000e0000000-00000000e7ffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 e9 29 07 05 10 00 00 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 08 08 00 f0 00 00 00
20: f0 ff 00 00 01 e0 f1 e7 00 00 00 00 00 00 00 00
30: 00 00 00 00 88 00 00 00 00 00 00 00 0a 01 02 00

00:1a.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 20
	Region 4: I/O ports at 2100 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 37 29 05 00 90 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00

00:1a.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 21
	Region 4: I/O ports at 2120 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 38 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 02 00 00

00:1a.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 22
	Region 4: I/O ports at 2140 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 39 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 03 00 00

00:1a.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 (rev 02) (prog-if 20)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 22
	Region 0: Memory at eb104800 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ehci_hcd
00: 86 80 3c 29 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 48 10 eb 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 03 00 00

00:1b.0 Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio Controller (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 21
	Region 0: Memory at eb100000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: <access denied>
	Kernel driver in use: HDA Intel
	Kernel modules: snd-hda-intel
00: 86 80 3e 29 06 01 10 00 02 00 03 04 10 00 00 00
10: 04 00 10 eb 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00

00:1c.0 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=28, subordinate=28, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: 80000000-801fffff
	Prefetchable memory behind bridge: 0000000080200000-00000000803fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 40 29 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 28 28 00 30 30 00 00
20: 00 80 10 80 21 80 31 80 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 02 00

00:1c.4 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=34, subordinate=34, sec-latency=0
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: 80400000-805fffff
	Prefetchable memory behind bridge: 0000000080600000-00000000807fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 48 29 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 34 34 00 40 40 00 00
20: 40 80 50 80 61 80 71 80 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 02 00

00:1c.5 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 6 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=3f, subordinate=3f, sec-latency=0
	I/O behind bridge: 00005000-00005fff
	Memory behind bridge: eb000000-eb0fffff
	Prefetchable memory behind bridge: 0000000080800000-00000000809fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 4a 29 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 3f 3f 00 50 50 00 00
20: 00 eb 00 eb 81 80 91 80 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 05 02 02 00

00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 20
	Region 4: I/O ports at 2160 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 34 29 05 00 90 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 61 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00

00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 21
	Region 4: I/O ports at 2180 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 35 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 81 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 02 00 00

00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 22
	Region 4: I/O ports at 21a0 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 36 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: a1 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 03 00 00

00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 02) (prog-if 20)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at eb104c00 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ehci_hcd
00: 86 80 3a 29 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 4c 10 eb 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00

00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92) (prog-if 01)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=10, subordinate=10, sec-latency=32
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
00: 86 80 4e 24 07 01 10 00 92 01 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 10 10 20 f0 00 80 22
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 02 00

00:1f.0 ISA bridge: Intel Corporation 82801IR (ICH9R) LPC Interface Controller (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel modules: iTCO_wdt
00: 86 80 16 29 07 01 10 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:1f.2 RAID bus controller: Intel Corporation 82801 SATA RAID Controller (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 29
	Region 0: I/O ports at 2200 [size=8]
	Region 1: I/O ports at 2210 [size=4]
	Region 2: I/O ports at 2208 [size=8]
	Region 3: I/O ports at 2214 [size=4]
	Region 4: I/O ports at 21c0 [size=32]
	Region 5: Memory at eb104000 (32-bit, non-prefetchable) [size=2K]
	Capabilities: <access denied>
	Kernel driver in use: ahci
	Kernel modules: ahci
00: 86 80 22 28 07 04 b0 02 02 00 04 01 00 00 00 00
10: 01 22 00 00 11 22 00 00 09 22 00 00 15 22 00 00
20: c1 21 00 00 00 40 10 eb 00 00 00 00 3c 10 08 13
30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 02 00 00

01:00.0 VGA compatible controller: nVidia Corporation G84 [Quadro FX 1700] (rev a1)
	Subsystem: nVidia Corporation Device 049a
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at ea000000 (32-bit, non-prefetchable) [size=16M]
	Region 1: Memory at c0000000 (64-bit, prefetchable) [size=512M]
	Region 3: Memory at e8000000 (64-bit, non-prefetchable) [size=32M]
	Region 5: I/O ports at 1100 [size=128]
	Capabilities: <access denied>
	Kernel driver in use: nouveau
	Kernel modules: nvidiafb, nouveau
00: de 10 0f 04 07 00 10 00 a1 00 00 03 10 00 00 00
10: 00 00 00 ea 0c 00 00 c0 00 00 00 00 04 00 00 e8
20: 00 00 00 00 01 11 00 00 00 00 00 00 de 10 9a 04
30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 00 00

08:00.0 Non-VGA unclassified device: Texas Instruments Device b004 (rev 01)
	Subsystem: Spectrum Signal Processing Device 8320
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 10
	Region 1: Memory at e0000000 (32-bit, prefetchable) [size=32M]
	Region 2: Memory at e2000000 (32-bit, prefetchable) [size=32M]
	Region 3: Memory at e4000000 (32-bit, prefetchable) [size=32M]
	Region 4: Memory at e6000000 (32-bit, prefetchable) [size=32M]
	Capabilities: <access denied>
00: 4c 10 04 b0 07 01 10 00 01 00 00 00 10 00 00 00
10: 00 00 00 00 08 00 00 e0 08 00 00 e2 08 00 00 e4
20: 08 00 00 e6 00 00 00 00 00 00 00 00 fb 12 20 83
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00

3f:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5755 Gigabit Ethernet PCI Express (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 30
	Region 0: Memory at eb000000 (64-bit, non-prefetchable) [size=64K]
	Expansion ROM at <ignored> [disabled]
	Capabilities: <access denied>
	Kernel driver in use: tg3
	Kernel modules: tg3
00: e4 14 7b 16 06 04 10 00 02 00 00 02 10 00 00 00
10: 04 00 00 eb 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 49 3f 48 00 00 00 00 00 00 00 05 01 00 00
    Fullscreen 4682.tiBars.txt Download 
    00:00.0 Host bridge: Intel Corporation 82X38/X48 Express DRAM Controller
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel driver in use: x38_edac
	Kernel modules: x38_edac
00: 86 80 e0 29 06 01 90 20 00 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:01.0 PCI bridge: Intel Corporation 82X38/X48 Express Host-Primary PCI Express Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: e0000000-e2ffffff
	Prefetchable memory behind bridge: 00000000c0000000-00000000dfffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 e1 29 07 05 10 00 00 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 10 10 00 00
20: 00 e0 f0 e2 01 c0 f1 df 00 00 00 00 00 00 00 00
30: 00 00 00 00 88 00 00 00 00 00 00 00 0a 01 1a 00

00:06.0 PCI bridge: Intel Corporation 82X38/X48 Express Host-Secondary PCI Express Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=08, subordinate=08, sec-latency=0
	Memory behind bridge: e4400000-e44fffff
	Prefetchable memory behind bridge: 00000000e3000000-00000000e43fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 e9 29 07 05 10 00 00 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 08 08 00 f0 00 00 00
20: 40 e4 40 e4 01 e3 31 e4 00 00 00 00 00 00 00 00
30: 00 00 00 00 88 00 00 00 00 00 00 00 0a 01 02 00

00:1a.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 20
	Region 4: I/O ports at 2100 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 37 29 05 00 90 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00

00:1a.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 21
	Region 4: I/O ports at 2120 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 38 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 02 00 00

00:1a.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 22
	Region 4: I/O ports at 2140 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 39 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 03 00 00

00:1a.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 (rev 02) (prog-if 20)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 22
	Region 0: Memory at e4604800 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ehci_hcd
00: 86 80 3c 29 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 48 60 e4 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 03 00 00

00:1b.0 Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio Controller (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 21
	Region 0: Memory at e4600000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: <access denied>
	Kernel driver in use: HDA Intel
	Kernel modules: snd-hda-intel
00: 86 80 3e 29 06 01 10 00 02 00 03 04 10 00 00 00
10: 04 00 60 e4 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00

00:1c.0 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=28, subordinate=28, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: 80000000-801fffff
	Prefetchable memory behind bridge: 0000000080200000-00000000803fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 40 29 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 28 28 00 30 30 00 00
20: 00 80 10 80 21 80 31 80 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 02 00

00:1c.4 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=34, subordinate=34, sec-latency=0
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: 80400000-805fffff
	Prefetchable memory behind bridge: 0000000080600000-00000000807fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 48 29 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 34 34 00 40 40 00 00
20: 40 80 50 80 61 80 71 80 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 02 00

00:1c.5 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 6 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=3f, subordinate=3f, sec-latency=0
	I/O behind bridge: 00005000-00005fff
	Memory behind bridge: e4500000-e45fffff
	Prefetchable memory behind bridge: 0000000080800000-00000000809fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport
	Kernel modules: shpchp
00: 86 80 4a 29 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 3f 3f 00 50 50 00 00
20: 50 e4 50 e4 81 80 91 80 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 05 02 02 00

00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 20
	Region 4: I/O ports at 2160 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 34 29 05 00 90 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 61 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00

00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 21
	Region 4: I/O ports at 2180 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 35 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 81 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 02 00 00

00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 22
	Region 4: I/O ports at 21a0 [size=32]
	Capabilities: <access denied>
	Kernel driver in use: uhci_hcd
00: 86 80 36 29 05 00 90 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: a1 21 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 03 00 00

00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 02) (prog-if 20)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at e4604c00 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ehci_hcd
00: 86 80 3a 29 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 4c 60 e4 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00

00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92) (prog-if 01)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=10, subordinate=10, sec-latency=32
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
00: 86 80 4e 24 07 01 10 00 92 01 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 10 10 20 f0 00 80 22
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 02 00

00:1f.0 ISA bridge: Intel Corporation 82801IR (ICH9R) LPC Interface Controller (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel modules: iTCO_wdt
00: 86 80 16 29 07 01 10 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:1f.2 RAID bus controller: Intel Corporation 82801 SATA RAID Controller (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 29
	Region 0: I/O ports at 2200 [size=8]
	Region 1: I/O ports at 2210 [size=4]
	Region 2: I/O ports at 2208 [size=8]
	Region 3: I/O ports at 2214 [size=4]
	Region 4: I/O ports at 21c0 [size=32]
	Region 5: Memory at e4604000 (32-bit, non-prefetchable) [size=2K]
	Capabilities: <access denied>
	Kernel driver in use: ahci
	Kernel modules: ahci
00: 86 80 22 28 07 04 b0 02 02 00 04 01 00 00 00 00
10: 01 22 00 00 11 22 00 00 09 22 00 00 15 22 00 00
20: c1 21 00 00 00 40 60 e4 00 00 00 00 3c 10 08 13
30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 02 00 00

01:00.0 VGA compatible controller: nVidia Corporation G84 [Quadro FX 1700] (rev a1)
	Subsystem: nVidia Corporation Device 049a
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at e2000000 (32-bit, non-prefetchable) [size=16M]
	Region 1: Memory at c0000000 (64-bit, prefetchable) [size=512M]
	Region 3: Memory at e0000000 (64-bit, non-prefetchable) [size=32M]
	Region 5: I/O ports at 1100 [size=128]
	Capabilities: <access denied>
	Kernel driver in use: nouveau
	Kernel modules: nvidiafb, nouveau
00: de 10 0f 04 07 00 10 00 a1 00 00 03 10 00 00 00
10: 00 00 00 e2 0c 00 00 c0 00 00 00 00 04 00 00 e0
20: 00 00 00 00 01 11 00 00 00 00 00 00 de 10 9a 04
30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 00 00

08:00.0 Multimedia controller: Texas Instruments Device b005 (rev 01)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 10
	Region 0: Memory at e4400000 (32-bit, non-prefetchable) [size=1M]
	Region 1: Memory at e4200000 (32-bit, prefetchable) [size=1M]
	Region 2: Memory at e4000000 (32-bit, prefetchable) [size=2M]
	Region 3: Memory at e3000000 (32-bit, prefetchable) [size=16M]
	Region 4: Memory at e4310000 (32-bit, prefetchable) [size=4K]
	Region 5: Memory at e4300000 (32-bit, prefetchable) [size=64K]
	Capabilities: <access denied>
00: 4c 10 05 b0 07 01 10 00 01 00 80 04 10 00 00 00
10: 00 00 40 e4 08 00 20 e4 08 00 00 e4 08 00 00 e3
20: 08 00 31 e4 08 00 30 e4 00 00 00 00 00 00 01 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00

3f:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5755 Gigabit Ethernet PCI Express (rev 02)
	Subsystem: Hewlett-Packard Company Device 1308
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 30
	Region 0: Memory at e4500000 (64-bit, non-prefetchable) [size=64K]
	Expansion ROM at <ignored> [disabled]
	Capabilities: <access denied>
	Kernel driver in use: tg3
	Kernel modules: tg3
00: e4 14 7b 16 06 04 10 00 02 00 00 02 10 00 00 00
10: 04 00 50 e4 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 08 13
30: 00 00 49 3f 48 00 00 00 00 00 00 00 05 01 00 00

    By the way, I would like to remind you that we are working on the C6670 and perhaps this is what is making the difference.

    Aymeric

  • 0 in reply to aymeric dupont
    Expert 2145 points

    Hi Eric,

    We ran tests on Friday with the C6670 EVM and with our own board and we have some updates and some questions.

    With our own board, the code changes suggested by you do NOT cause BAR0 to be visible.

    With the EVM, the code changes suggested by you cause BAR0 to be visible from the Linux PC.

    Could you explain why bit 28 of PCIE_LINK_STAT_CTRL needs to be set to 1? The description of this bit on pg 177 of sprugs6c.pdf is:

    “Slot Clock Configuration. Writable from internal bus interface. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector.”

    In the case of our board, our hardware designer specified that this bit should be set to 0. In your recommended code changes you say this should be set to 1.  We will need to know why you recommended this and how this might affect our design.

    A second question: Why is the order of operations to set the bar important?

    Third question: Why are the masks that we set (1M -1M -1M and 4M) being defaulted by the EVM to 32-32-32-32?

    Thanks,

    Geraldine

  • 0 in reply to Geraldine Maclear
    TI__Guru* 95265 points

    Geraldine,

    Sorry to learn the suggested setup didn't work on your platform.

    For Q1, Is correct your PCIE card uses the SS clock from Linux machine? If yes (as our EVM), you need to set COMMON_CLK_CFG bit, EXT_SYNC bit and SLOT_CLK_CFG bit in LINK_STAT_CTRL register to indicate the common clock usage. See http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/252585/888391.aspx. Since you HW engineer suggest this bit to 0, can you check with him the background?

    For Q2, I am not sure why order is important, still investigating.

    For Q3, Is 32-32-32-32 what you saw on your card? 1-1-2-16 on EVM?

    "With the EVM, the code changes suggested by you cause BAR0 to be visible from the Linux PC." ===========> Do you mean without code change, BAR0 is gone on 6670 EVM?

    Regards, Eric

  • 0 in reply to lding
    Expert 2145 points

    Hi Eric, I have an update and an answer to one question. Regarding Q1 above I have asked our hardware engineer for his input.

    "With the EVM, the code changes suggested by you cause BAR0 to be visible from the Linux PC." ===========> Do you mean without code change, BAR0 is gone on 6670 EVM?   ====> YES, that is correct.


    We have done some more experiments and found that if we reduce the size of our EEPROM image from about 60KBytes to about 6KBytes, then the problem goes away. With this very small EEPROM image we can see BAR0 on the Linux PC. So it seems that loading and parsing the EEPROM image at boot time is taking too long and this is why the PCIe setup is not working correctly. We are gathering more data about the timing from monitoring the I2C bus. This bus shows bursts of activity based on processing of chunks. It seems like the gap between reading chunks is unexpectedly large. How long should we expect the RBL to take to process each chunk that is loaded from the EEPROM? Is this something you have measured on your system? Will this processing time impose some upper limit on how big an image can be which loads from EEPROM and sets up the PCIe bus? Our test image size of 6KBytes is unfortunately too small for what we need to do during this first boot stage.

    Thanks,
    Geraldine

  • 0 in reply to Geraldine Maclear
    Expert 2145 points

    Another answer...

    “For Q1, Is correct your PCIE card uses the SS clock from Linux machine? …”

    The answer is:

    -      When our board is in a Linux machine, it uses the PCIE clock from that machine.

    -      When our board is in a VPX system, the PCIE clock from the SBC is not available and the board uses the PCIE clock generated by the VPX carrier.