Hi,
I am using AM3358 EVM board able to boot with TI SDK 3.2 kerne and suspend/resume feature works fine.But we have ported the AM3358 machine to Custom kernel version 2.6.35 which is also booting and working fine.
Currently we tried to test the suspend/resume support in the custom kernel which is not resuming after suspend.We are able to suspend/resume through GPIO0 when TI emulator is connected to arm-cortex-A8 core.Without connecting the emulator target is not resuming from the suspend state.
We further debug by connecting M3_wakupss core through emulator.We observed below error.
1.After bootup,once we give suspend (echo mem > /sys/power/state) and we stopped the M3 core ,checked the register info list in CCS.Found there is a exception number in the register xPSR.Since R0,R1 registers shows the address 0x44E000E0 we suspects the there is issue with CM_PER_L3_CLKCTRL module.We added following lines to pm33xx.c at am33xx_pm_suspend function.
gpio1_oh = omap_hwmod_lookup("gpio1"); /* WKUP domain GPIO */
tptc0_oh = omap_hwmod_lookup("tptc0");
tptc1_oh = omap_hwmod_lookup("tptc1");
tptc2_oh = omap_hwmod_lookup("tptc2");
cpsw_oh = omap_hwmod_lookup("cpgmac0");
lcdc_oh = omap_hwmod_lookup("lcdc");
tpcc_oh = omap_hwmod_lookup("tpcc");
mmc_oh = omap_hwmod_lookup("mmc3");
omap_hwmod_enable(usb_oh);
omap_hwmod_enable(gpmc_oh);
omap_hwmod_enable(gpio1_oh);
omap_hwmod_enable(tptc0_oh);
omap_hwmod_enable(tptc1_oh);
omap_hwmod_enable(tptc2_oh);
omap_hwmod_enable(cpsw_oh);
omap_hwmod_enable(lcdc_oh);
omap_hwmod_enable(tpcc_oh);
omap_hwmod_enable(mmc_oh);
omap_hwmod_idle(usb_oh);
omap_hwmod_idle(gpmc_oh);
omap_hwmod_idle(tptc0_oh);
omap_hwmod_idle(tptc1_oh);
omap_hwmod_idle(tptc2_oh);
omap_hwmod_idle(cpsw_oh);
omap_hwmod_idle(lcdc_oh);
omap_hwmod_idle(tpcc_oh);
omap_hwmod_idle(mmc_oh);
Please find the register details below.
Core Registers
PC 0x00000CA6 Core Register: Program Counter
SP 0x00080F60 Core Register: General Purpose Register 13 - Stack Pointer
LR 0x00000CD3 Core Register: General Purpose Register 14 - Link Register
xPSR 0x81000032 Core Register: Stores the status of interrupt enables and critical processor status signals
N 1 Stores bit 31 of the result of the instruction. In other words stores the sign of the number
Z 0 Is set to 1 if the result of the operation is zero else stays 0
C 0 Stores the value of the carry bit if it occurred in an addition or the borrow bit in a subtraction. In a shift stores the last bit shifted out.
V 0 Set to 1 if an overflow occurred
Q 0 Indicates whether an overflow/saturation occurred in the enhanced DSP instructions
ICI_IT_2 00 ICI/IT - bit26-bit25
T 1 Thumb State
RESV 00000000 Reserved
ICI_IT_1 000000 ICI/IT - bit15-bit10
RESV2 0 Reserved
EXCEPTION 000110010 Exception Number
R0 0x44E000E0 Core Register: General Purpose Register 0
R1 0x44E000E0 Core Register: General Purpose Register 1
R2 0x00000000 Core Register: General Purpose Register 2
R3 0x00010000 Core Register: General Purpose Register 3
R4 0x00000000 Core Register: General Purpose Register 4
R5 0x00000000 Core Register: General Purpose Register 5
R6 0x00000000 Core Register: General Purpose Register 6
R7 0x00080F60 Core Register: General Purpose Register 7
R8 0x00000000 Core Register: General Purpose Register 8
R9 0x00000000 Core Register: General Purpose Register 9
R10 0x00000000 Core Register: General Purpose Register 10
R11 0x00000000 Core Register: General Purpose Register 11
R12 0x00000000 Core Register: General Purpose Register 12
R13 0x00080F60 Core Register: General Purpose Register 13
R14 0x00000CD3 Core Register: General Purpose Register 14
MSP 0x00080F60 Core Register: MSP Register
PSP 0x00000000 Core Register: PSP Register
DSP 0x00000000 Core Register: DSP Register
CTRL_FAULT_BASE_PRI 0x00000000 Core Register: CM3 Special Registers
Please let us know how to debug M3 core further?Can you share the source code of M3_Wkup firmware?
Are we missing any clock/power initialisation in linux kernel running at A8 core?
Regards
Yogavanan
