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PCIe Memory Read problem

Delared Delared
Expert 1945 points

Hi,

I have a problem with PCIe Memory Read from/to DSPC6678 using a PCIe switch.

So when I perform Memory Write transactions, test passed OK (using CPU & EDMA)

But that is non Ok with MRd (i get a wrong/random data)

 My programs are based on example project in MCSDK/ PDK provided by TI, and I can perform both MWr and MRd correctly using the Dual BOC.

side switch, i think made all necessary config (enumeration...).

May I ask, when I add the PCIe switch there are some modifications needed on DSP sides (configuration registers, BAR, Outbound, Inbound…).

 all suggestion will be appreciated.

  • 0
    TI__Guru* 95265 points

    Delared,

    Here is some earlier discussion for PCIE switch http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/256253.aspx. Is your switch in transparent mode? If the PCIE write works both ways, I think PCIE read should works as well. When read error happened, do you see any failure pattern? And what are the real data content in DSP memory looks like?

    Regards, Eric Post

  • 0 in reply to lding
    Expert 1945 points

    Eric,

    here some error reposrting:

    - the port EP link is down

    - the port RC detects parity and 8B/10B error

    i m trying to rad data from a buffer in EP side (0,1,3,4,5....) but i receive a wrong data (1610612736, 1, 1610612736,2,1610612736, 1610612736...0)

  • 0 in reply to Delared Delared
    TI__Guru* 95265 points

    Delared,

    If the EP side link is down, then the data read is invalid. You need to fix the link first, why adding a switch caused parity error? Did the switch set up properly?

    Regards, Eric 

  • 0 in reply to lding
    Expert 1945 points

    Eric,

    As you said, i think also " If the PCIE write works both ways, I think PCIE read should works as well"

    before to perform any transaction, i make sure that the the DSP establish the link with the switch "link is up", so the status of the link pass to link is down just after i performed MRd transactions!!

    attached a figure shown the enumeration setup of the switch (that works very well with MWr , RC-to-EP and vice versa)

    Say that MRd is a non posted transaction, the completion packets should be routed to the requester based on its ID or something else (i think the switch do this automatically, however i'm looking if there are some other config. that should be added with MRd (non posted)).

    Please your suggestions of solution and any idea that could close that issue will be apreciated.