OMAP-L138 EMIFA Timing

Jazz Kuo

Other Parts Discussed in Thread: OMAP-L138

Hello,

I use OMAP-L138 EMIFA CS2 to access MRAM, and the CE2CFG is set 0x04224225. My program is following, and using scope to probe the EMA_CS2 signal.

Why CPU lag 175nsec every time after EMIFA read cycle ? The result is same by EMIFA CS4 to access another device in my hardware.

#define MRAM_START_ADDR 0x60000000

    unsigned short uReadValue;
   unsigned short * pPt = ((unsigned short *)MRAM_START_ADDR);
   while(1){
        // read cycle
        uReadValue = *pPt;
       uReadValue = *pPt;
        // write cycle
        *pPt = 0x5A5A;
       *pPt = 0x5A5A;
    }

over 12 years ago

0 Sunil Kamath over 12 years ago

TI__Expert 7470 points

Jazz,

This has to do with data transfer latencies through the system interconnect. Read transactions are usually more costly (in clock cycles) than writes. For writes, the command and data flow together and can be thought of as "fire-and-forget" in nature. Once a write transaction leaves the master/initiator boundary (ex: sitting in a bridge or an end point's buffer or FIFO), the initiator can proceed to the next write (even before the previous write reaches its final destination). For reads, a read command pends until a read response/data returns. So in general, the initiator cannot issue a new read/write command until the previous read command's response reaches the master/initiator.

You may want to take a close look at the information in the wiki page below and linked pages to gain a better understanding of the data transfer through the interconnect:

http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SOC_Architecture_and_Throughput_Overview

Regards,

Sunil

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OMAP-L138 EMIFA Timing