MCASP Design on AM335X Startup Board

Hi Hanumanji,

By "Startup Board" do you mean the AM335x StarterKit or some other board? I need to know which schematic you are referring to. There is no McASP signal "BCLK"

Also please let me know what software you are using - the AM335x SDK, the AM335x StarterWare? Which version?

In the kernel board file, the McASP signals are pinmuxed, depending on which board is used:

/* Module pin mux for mcasp1 */
static struct pinmux_config mcasp1_pin_mux[] = {
    {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
    {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
    {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
    {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
                        AM33XX_PIN_INPUT_PULLDOWN},
    {NULL, 0},
};

Inside StarterWare, the function McASP1PinMuxSetup() does the pinmuxing for the McASP:

/**
 * \brief   This function selects the McASP instance 1 pins
 *          
 * \param   None
 *
 * \return  TRUE/FALSE.
 *
 * \note    This muxing depends on the profile in which the EVM is configured.
 */
unsigned int McASP1PinMuxSetup(void)
{
    unsigned int profile;
    unsigned int status = FALSE;

    profile = EVMProfileGet();

    switch (profile)
    {
        case 0:
        case 3:
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
                          CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
                          | MCASP_SEL_MODE;            
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
                          CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
                          | MCASP_SEL_MODE;            
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
                          CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
                          | MCASP_SEL_MODE;            
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) =
                          CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE
                          | MCASP_SEL_MODE;            
            status = TRUE;
        break;

        default:
        break;
    }
    
    return status;
}

In both cases only four pins are used. For the ZCZ package of the processor (please refer to the datasheet) these pins/balls are:

mii1_crs -> H11
mii1_rx_er -> J15
mii1_col -> H16
rmii1_ref_clk -> H18

Best regards,
Miroslav