Hello.
I measured GPMC XIP Timing on TMDXEVM3358.
The /CS0 wave is different from TRM definition.
Question:
- I think tCEon = 0.
How do you think about this? (Is this typo of TRM?)
- How do you think about 6nsec delay existing on the /CS0?
my setting is :
SYSBOOT[15:0] = 0100000100011010b
TRM description:
Actual wave:
Best regards, RY
Hello,
I captured the GPMC registers after XIP boot.
The actual value was the CSEXTRADELAY = 1h, and CSONTIME = 0h.
TRM should specifies that the tCEon = 1/2 gpmc_fclk.
I would like to request this to the "Submit Documentation Feedback".
Best regards, RY
Fig. CSEXTRADELAY=1h, and CSONTIME = 0h after XIP boot.
Hi.
I have requested by important customer to correct the TRM.
Could you correct the wave form and table like below?
Best regards, RY
Biser-san,
Sorry to trouble you..
I told to our customer what TRM is updated .
But, they say that it have mistake.
From above figure, 1/2 clock cycle = 10nsec.
But, actually the delay is 5nsec.
So it should be "1/4" if you specifies using "clock cycles".
Or, you should specify both "1/2 GPMC_FCLK" and "GPMC_FCLK cycle is 10nsec".
Can you fix it to the TRM in the next update?
Best regards, RY
Biser-san,
Thank you so much for your reply.
I agree to your considering.
But, TRM does not specify "CSEXTRADELAY=1". (It's just my result.)
Instead it specifies clearly "tCSEXTRADELAY=1/2 clock cycle".
All of the user will feel tCSEXTRADELAY=10nsec.
How do you think?
Best regards, RY
Biser-san,
You are right.
Actually, since the GPMCFCLKDIVIDER is 0h, GPMC clock cycle is 100MHz.
However, in this condition(clock cycle=100MHz), all the timing parameter in Table 26-8 is wrong.
To correct description, the following specification must be specified:
- TIMEPARAGRANULARITY=1h. (Add this condition)
- GPMC clock cycle = 100MHz. (Fix this condition from 50MHz.)
Could you send this post to TRM team?
Best regards, RY
