I'm using 6748&CCS v5.3,I want to modify the bit GIE in Control status register(CSR),but I can't find the address of CSR,I can't use any API for this
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I'm using 6748&CCS v5.3,I want to modify the bit GIE in Control status register(CSR),but I can't find the address of CSR,I can't use any API for this
Junhao Zhuge,
On the TI Wiki Pages, you can search for "c6000 workshop" (no quotes) to find the C6000 Workshop with SYS/BIOS. It walks you through the process of using the many features of SYS/BIOS, which are designed to give you important features for complex applications and simple functions to handle many of the system requirements such as Hardware Interrupts (Hwi module).
You will find a chapter covering the Hwi module, and it discusses how to do exactly what you want to do with the following functions:
Hwi_disable() Global INTs disable
Hwi_enable() Global INTs enable
Hwi_restore() Global INTs restore
Regards,
RandyP
Junhao Zhuge,
TI supplies the BIOS APIs so that you do not have to study deeply the documentation of the device. We do this to save you a lot of time and debugging.
If you cannot use these APIs, then you can refer to the CPU & Instruction Set Reference Guide for your device. It explains the assembly instruction MVC and how you can use that instruction to access the control registers in the DSP core.
The CSR is not a Memory Mapped Register, so it is not possible to access it through normal C instructions. You cannot set a pointer to use for reads/writes, but must use the MVC assembly instruction.
The easiest way to do this is to use the BIOS API.
The next way would be to use the BIOS API, and then use the CCS debugger to step into the API to see what assembly instructions it uses. Then you can write a small assembly function to implement that sequence of instructions. That assembly function will then by your own API, unless you prefer to label it differently.
Regards,
RandyP
RandyP,
Thanks for your careful answer,but this cannot resole my problem now.I'm using CCS v5.3 with BIOS v6.35 NDK v2.22 and NSP v2.10.We are the general scheme is this:
Now I want to do a signal acquisition and transmission via Ethernet model.Require every 1ms to occur 15us timer interrupt,and the number of 15us Timer interrupt is 16.Every 15us interrupt to open a 16-bit SPI and exit.Wait the interrupt of SPI come read the data of SPIBUF.And every 10ms send the data through Ethenet.So my 15 us Timer and SPI interrupt must be the highest priority.Now my problem is NDK used the Rx and Tx interrupt of EMAC during running that two interrupt ISR CPU disable the Global interrupt by BIOS,and result CPU extend 15us and SPI interrupt response time.Finally result is 15us Timer is Inaccurate,the data of send is wrong.
I have find the way to resole the problem that use interrupt nesting.It need to enable or restore global interrupt.Now I have find the file of NDK drivers,it loacte in C:\ti\nsp_1_10_01_06\packages\ti\drv\omapl138\ethdriver.c But I want to modify it by C language,and I cannot add Header file inside.So I modify CSR direct only!
Above is my whole problem,if you have solution,tell me please quickly!
For CSR access, suggest you look at the special features of the compiler. See:
TMS320C6000 Optimizing Compiler v7.4
User's Guide
Literature Number: SPRU187U July 2012
6.5.2 The cregister Keyword
7.5.8 Using Intrinsics for Interrupt Control and Atomic Sections
You could include c6x.h and access CSR as a special extern variableor use the intrinsics _disable_interrupts(), _enable_interrupts() and _restore_interrupts(). Never used any of these myself. I don't know enough of BIOS to say if you are breaking the BIOS way of doing things. No guarantees.