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srio 8bit deviceID problem

I tried to communicate with FPGA using EVM board. When I set device ID to be 16bit ,everything goes well. But when I changed LSU_REG4 with ID length=0 ,8bit device ID, writing LSU_REG5 seems generated no transmission.  What is the problem?

Thanks a lot

  • You are correct that all you need to do is program LSU_Reg4 ID length field to send 8b or 16b IDs.  That is the only requirement.  Are you sure the FPGA is setup to receive 8b IDs?  How do you know they aren't being transmitted?  Try to send a NWRITE_R transaction and see what the CC is.

    Regards,

    Travis

  • We looked on fpga side of communication. When 16bit ID is used, we can actrully see the coming package and everything is just right. But when 8bit ID is used, nothing can be catched, it seemed no package is submitted. And I tried to loopback on my own device, 16bit ID can transmit data right, but with 8bit ID nothing happens, the destination data keeps 0.

    What is going on then?

    Thanks

  • The ID size is a RapidIO transport layer packet field.  Are you saying that you look in the memory location of the FPGA and you don't see the memory contents as expected when using 8b IDs?  Or is there another method for determining failure when you say "nothing can be catched"?

    yu fei said:
    And I tried to loopback on my own device,

    Is your own device the DSP in lookback?  If so, are you setting promiscuous mode on the receive?  If not, you must make sure the DestID in the packet is the same as the one used in RIO_BASE_ID or BRR registers.

  • We tried to look at data transmitted by DSP on FPGA side online. When 8bit ID is used, FPGA received nothing at all, not a single package is transmitted, but 16bit ID package is sent and FPGA can cache the data and package head online. I am sure loopback mode is not active.

  • Are you still having the issue?  If it would be helpful, we can send an SRIO DSP example that works in loopback with 8b IDs.  Then you know the configuration of the DSP is correct and you can debug on the FPGA side.  Let us know.

    Regards,

    Travis

  • That would be very helpful. Thanks a lot.

  • yu fei,

    Sorry for any delay; attached is a simple DIO loopback example using an 8-bit DEST ID. As Travis pointed out, you'll need to set up the BRR registers properly.

    -Ivan

    4540.srio_dio_C6678_8bit.zip