How to deal with C64x+ DSP cache

Sergey Slyusarenko

Hello,

I'm developing an image processing application using Codec Engine. For improving perfomance I think it would be good to use DSP cache. I would like to copy buffer from DDR2 memory to DSP cache, do some processing with this buffer, and return new data to another buffer allocated in DDR memory. As far as I can see BCACHE API is what I need. But I don't quite understand how to use this API for my purposes. What functions and on what sequence do I need to invoke them? Some example codes would be appreciated.

Thanks,
Sergey

over 13 years ago

0 Cvetolin Shulev-XID over 13 years ago

TI__Guru 65405 points

Hi Sergey,

You can look at the following tutorial about Porting GPP code to DSP and Codec Engine. You can find in the attachment to this tutorial an example project (JPEGDEC_Wrapper.zip, TestAppDecoder.c) and see how to use BCACHE APIs.

http://processors.wiki.ti.com/index.php/Porting_GPP_code_to_DSP_and_Codec_Engine

In addition you can look at the article about how to enable 64x+ cache

http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache

Tsvetolin Shulev

0 Sergey Slyusarenko over 13 years ago in reply to Cvetolin Shulev-XID

Prodigy 215 points

Hi Tsvetolin,

Thanks for references. According with JPECDEC_Wrapper example I do the following:

BCACHE_Size size;
size.l1psize = BCACHE_L1_32K;
size.l1dsize = BCACHE_L1_32K;
size.l2size = BCACHE_L2_64K;
BCACHE_setSize(&size);
BCACHE_setMar((Ptr *)0x80000000, 0x10000000, BCACHE_MAR_ENABLE);
BCACHE_wbInvAll();

...

BCACHE_inv(buf, width*height, TRUE);
BCACHE_inv(kernel, 128, TRUE);

while (i < count)

{
for (j = 0; j < height-2; j++)
convI(buf+j*width, buf+j*width, width, kernel, 0);

}

BCACHE_wbInv(buf, width*height, TRUE);

BCACHE_wbInvAll();

Sizes of all buffers are divisible 128. In .tci file:

var device_regs = {
l1PMode: "32k",
l1DMode: "32k",
l2Mode: "64k"
};

bios.GBL.C64PLUSMAR128to159 = 0x0000ffff;

Execution time of algorithm with or without using BCACHE API is the same. How to correctly use this api to take advantages of L1/L2 cache?

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How to deal with C64x+ DSP cache