6678 initialization after soft reset

Sergey,

In order to retain the data in the DDR through a soft reset you will need to take a few steps before asserting the reset:

1. Enable reset isolation for the power module that the DDR is in (bit 12 = 0x1 in the MDCTL2 register)
   1. Section 3.2.8 of the Power Sleep Controller User Guide describes the MDCTLy register where bit 12 corresponds to the reset isolation enable or disable
   2. From section 7.3.2 of the 6678 Data Manual you will see that the DDR EMIF is in module 2 (so you will need to alter bit 12 in the MDCTL2 register)
2. Put the DDR into self-refresh mode (bits 10:8 = 0x2 in the PMCTL register)
   1. Bits 10:8 of the Power Management Control Register (PMCTL) specified in section 4.8 of the DDR3 Memory Controller User Guide will need to be set to 0x2 in order to put the DDR into self-refresh mode

Since reset isolation will allow the DDR clocks to continue to run through a soft reset you will also need to find a way to NOT reinitialize the DDR PLL after the soft reset that you issue. One way to achieve this would be to check the reset type in the Reset Type Status Register (RSTYPE, specified in section 7.5.6.2 of the 6678 Data Manual) and if the reset type is not POR then you should not initialize the DDR PLL. 

This way you could have some sort of flag in your secondary boot loader that checks the reset type and if it is a POR then the DDR PLL is configured but if the reset type is not a POR then the DDR PLL configuration can be skipped since the configuration should survive through the soft reset because of the reset isolation. 

Let me know if there are any other questions,

Jason Reeder

Hi Jason.

Following your advice I wrote a program that initializes the processor carries out the test memory and then do soft reset. This program is stitched in EEPROM, which leads to cyclical reseting.

8284.softreset_test.tar.gz

By launching this program on the various custom boards (with 6672, 74, 78 DSPS) I observed the following:

1. On some of the "conditionally good" boards, reset is successful, the data in the DDR3 is not lost. Directly at reset time,  DDR3 clock speed is slightly reduced, with  667MHz up to 550-350, but then recovered.

2. On some of the "conditionally bad" boards, slowing the clock frequency DDR3 also observed, but then after 480 mcs after the removal RESET_STATUS,  the clock  just off at all. Re-clock appears after about 4 ms when the RBL begins to read from the I2C EEPROM.

I made ​​the appropriate screenshots from the analyzer:

a)

where: 1 - yellow - DDR3 reference clock (input) 100 MHz

2 - green - DDR3 PLL output 667MHz

3 - pink - DSP RESET_STATUS

As seen in the figure, while DSP in reset, DDR3 clock frequency is changed, after the removal of DSP reset frequency is restored, but after about 480 mcs completely disappears.

b)

where: 1 - yellow - DDR3 PLL output

D0 - RESET STATUS

D1 - I2C SDA

D2 - I2C CLK

As seen in the figure, after the release of the reset, the  DDR3 clock is lost by 4 ms, and then, almost simultaneously with the beginning of reading I2C, PLL begins to run anew.

c)

this is a photo  of a DSP from one of the boards.

Additionally I would like to clarify about MAINPLL. In the datasheet for 6678 says that writing the non-zero entry in the RSISO prevents PLL reset.

However, in practice, I observe that the frequency drops to 100 MHz  after each reset. And in MAINPLL registers  bypass bit does not appear, but in the  PLL controller registers bit PLLEN shows that the PLL is off.

This behavior is observed at both "conditionally good" and "conditionally bad" boards.

Sergey,

Please see section 2.5.2.5.1 of the 6678 Data Manual to explain the behavior of the main PLL. This section explains that during boot, the main PLL will be configured in bypass mode while performing the initial read from I2C. 

You say that the DDR data is not lost on "conditionally good" boards and the DDR PLL is retained as well. Can you explain how you define a conditionally good board versus a conditionally bad board? Are all of your analyzer screenshots from conditionally bad boards?

Thanks,

Jason Reeder

Hi Jason.

All screenshots are from bad boards. On good boadrs ddr3 pll does not stop after  reset. It only slowdown while reset_status active and restore normal clock immediately after removal of reset.

I have:

 14 boards on 6672 - all are bad;

12 boards on 6674 - 8 bad, 4 good:

20+ boadrs on 6678 - 2 bad.

 All these boards are custom boards based on the reference design from TI.

I misspelled information on the 6674 boards. All 12 boards were bad. But in the four 6674 replaced by 6678 and they became good.

Sergey,

I am going to talk to some people on my team about your issue and I will get back to you as soon as possible.

Thanks,

Jason Reeder

Sergey,

After talking to some of my team members I think that you may benefit from placing the DDR PLL into bypass mode before the reset and then reconfiguring the DDR PLL after reset. So the steps should now look like this:

1. Enable DDR reset isolation
2. Place the DDR into self-refresh mode
3. Put the DDR PLL into bypass mode
   1. Set the BYPASS bit to 1 in the DDR3PLLCTL0 register
4. Reset the device
5. Reconfigure the DDR PLL (but do not reconfigure your other DDR configuration registers)

The reset isolation should protect your DDR configuration registers so you should be able to move your reset type check just below the SetDDR3PllConfig() function in your DDR3Init function in your ddr3.c file of your project. It should look something like this:

You will also need to remove the reset type check from your SetDDR3PllConfig() function in order to let the DDR PLL be reconfigured. 

Sorry for the delay and let me know if you have any other questions,

Jason Reeder