Hi, I do not know if this is the correct forum to post to but if I am wrong please redirect me to the appropriate one.
We are trying to run some benchmarks on a few algorithms on a DM6435 processor.
We are comparing cycle accurate simulations of our algorithms against data measured directly on a custom board.
Both the simulator and the board are ran @500Mhz without any cache enabled. All program and data are stored in external DDR2 accessed through EMIF.
I would like to stress that the configuration of the PLL/CACHES/DDR2 are performed through the same c source code functions both in emulation and in simulation.
We use TSCH and TSCL timestamps to measure code execution.
What we are seeing is that there is a factor of 6 (x6) difference between the simulated and the emulated results.
So, my question is has anybody observed anything similar?
Is the real time stamp counter (TSCL,TSCH) running at the same speed as the main system clock ?
Is the cycle accurate simulator "really" running at the true speed or clock tick results have to be scaled ?
Thanks a lot,
Todor