PLL doesn't lock

Hi,

What is the list of changes? Is anything related to PLL? Have you check JTAG load program and run it?

Regards,

Hyun

Thanks for the reply.

The changes:

1. changed DDR3 from EMIF0 32bit to EMIF0 16bit+EMIF1 16 bit. total capacity doubled to 1GB
This is an effort to get rid of resizer overflow issue.
The PLL issue happens before DDR initialization, so I double this is the cause. 

2. changed main clock from crystal to oscillator.
But I tried changing it back, no difference. 

I am using CCS5 to debug it, the rom boot loader loads uboot in MMC without any problem, but it always hangs at pll_config().
As I mentioned, previous board works fine. 

update: I found the POR input was not right. I am checking the circuit right now.

Fixed POR issue， which is caused by power supply, right now it stucks on ddr_pll_config(),

the PLL status register reads back 0xC00001E9, so that means "Reference input loss", what could cause this?

Input oscillator is 20Mhz, DDR is running at 400Mhz.

I also tried slowing down the DDR to 200Mhz, same thing.

anybody? please~

Hi Hongfeng,

Did you perform the DDR leveling? See below for more info:

http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling

Can you also run memory test from u-boot: http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init#Run_mtest

target# mtest 0x80800000 0xA0000000 0xaa55aa55 3 (referred as Test A)
target# mtest 0xA0000000 0xC0000000 0xaa55aa55 3 (referred as Test B)

Regards,
Pavel

Pavel:

At this point, I don't think it's related to SW leveling. because it's stuck at prcm_init(), which is before function config_ti814x_ddr().

The DDR won't work anyway if the PLL doesn't even work.

Hongfeng,

Does you flow stuck at the below line?

../board/ti/ti8148/evm.c

prcm_init() -> ddr_pll_config -> pll_config()

/*
 * configure individual ADPLLJ
 */
static void pll_config(u32 base, u32 n, u32 m, u32 m2, u32 clkctrl_val)
{
    u32 m2nval, mn2val, read_clkctrl = 0;

    m2nval = (m2 << 16) | n;
    mn2val = m;

    /* by-pass pll */
    read_clkctrl = __raw_readl(base + ADPLLJ_CLKCTRL);
    __raw_writel((read_clkctrl | 0x00800000), (base + ADPLLJ_CLKCTRL));
    while ((__raw_readl(base + ADPLLJ_STATUS) & 0x101) != 0x101);       ----> stuck here?
    read_clkctrl = __raw_readl(base + ADPLLJ_CLKCTRL);
    __raw_writel((read_clkctrl & 0xfffffffe), (base + ADPLLJ_CLKCTRL));

Are you on EZSDK 5.05.02.00?

What is the revision of the DM814x device (PG2.x or 3.x)? http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/243814.aspx

Regards,
Pavel

Thanks for your reply.

1. the code was stuck at last line of pll_config()

while ((__raw_readl(base + ADPLLJ_STATUS) & 0x600) != 0x600);

2. I am using RDK3.2

3. If I change the boot loader to skip ddr_pll_config(), and let it run entirely from SRAM, then uboot will boot up ok.

4. Since other PLLs appear normal, and we did change the DDR part, I suspect the hardware is causing the problem, I am working with our PCB engineer trying to figure this out.

Regards,

Hongfeng

Yes, I also suspect that this is entirely hardware problem. Some pointers for hardware check:

http://processors.wiki.ti.com/index.php/DM814x_Hardware_Design_Guide

Regards,
Pavel

I found out what's triggering the problem, but it just makes things more confusing.

Previously, I lowered the DDR frequency to 200Mhz to rule out other possible causes, now I found that if I change it back to 400Mhz, the PLL works just fine. I tried other values: 300Mhz, 533Mhz, both are working fine. I don't know what's special about this 200Mhz?

Hongfeng,

I can not say for RDK, but for EZSDK DDR3 supports by default 400MHz and 533MHz.

ti-ezsdk_dm814x-evm_5_05_02_00/board-support/u-boot-2010.06-psp04.04.00.01/include/asm/arch-ti81xx/clocks_ti814x.h

#define DDR_PLL_400     /* Values supported 400,533 */

Regards,
Pavel

If its RDK, the DDR parameters (timing, latency etc) set in uboot are not applicable to 200 MHz.