Hi
Currently we have a customized design and we use DDR2 (MT47H64M16HR-25E) on the PCB
We see a strange behavior on the DDR2 that
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1. configure DDR2 (please see below settings)
2. Write data from 0x80000000 to 0x8000001F with 0x5a5aa5a5
3. read back 0x80000000 ~ 0x8000001F 100times and will get
80000000 = 5a5aa5a4 80000004 = 5a5aa5a4 80000008 = 5a5aa5a4 8000000c = 5a5aa5a4 80000010 = 5a5aa5a4 80000014 = 5a5aa5a4 80000018 = 5a5aa5a4 8000001c = 5a5aa5a4
80000000 = 5a5aa5a4 80000004 = 5a5aa5a5 80000008 = 5a5aa5a5 8000000c = 5a5aa5a5 80000010 = 5a5ba5a5 80000014 = 5a5ba5a5 80000018 = 5a5ba5a5 8000001c = 5a5ba5a5
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You can see that the bit0 will change from 0->1 but I have no idea what could make this happen ? Do you guys ever encounter such question ?
Below is my settings of DDR2:
#define DDR2_EMIF_READ_LATENCY 0x5 /* disable Dynamic Power Down */
#define DDR2_EMIF_TIM1 0x0666B3D6
#define DDR2_EMIF_TIM2 0x143731DA
#define DDR2_EMIF_TIM3 0x00000347
#define DDR2_EMIF_SDCFG 0x58805232 /* 0x59805232 */
#define DDR2_EMIF_SDCFG2 0x08000000
#define DDR2_EMIF_SDREF 0x00004950
#define DDR2_DLL_LOCK_DIFF 0x4
#define DDR2_RATIO 0x80
#define DDR2_INVERT_CLKOUT 0x00
#define DDR2_RD_DQS 0x40
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
#define DDR2_PHY_FIFO_WE 0x6A
#define DDR2_PHY_RANK0_DELAY 0x1
#define DDR2_IOCTRL_VALUE 0x18B
and our trace length is
DDR_CK Trace: 1.14903 (inch)
DDR_DQS Trace: 1.13877 (inc)
Appreciate if I could get feedback. Thanks a lot
