Timer cycles gets divided by 8 without main PLL Init

Any one looking into this??

Hi Sud,

I assume that it's connected to the boot and how the PLL is initialized, you can check the values according to the device user guide section 7.5 Main PLL and PLL Controller,

Thanks,

HR

Sud,

Which device are you using?

In the C6678, SYSCLK7 is a fixed divide-by-6 of the SYSCLK1 that clocks the DSP cores.

There may be a clock selector in the PSC that can change what clock source will drive the timer module, but I do not remember that being the case. You could look there to see if there is such a thing for your selected device.

Do you observe these results on an EVM or only on your own board?

Regards,
RandyP

Hi RandyP,

The device we are using is TMS320C6670. 

If there is such a clock selector in the PSC, how will the timer module know which input clock to select? Or to say, how will the timer module know that PLL is initialized and should take input clock from the PLL?

We observe this in the EVM. We executed the program without loading the GEL file. We observed that the timer profile values are divided by 8. After loading the GEL file, we got the expected timer values. We also confirmed that it was due to PLL not being initialized by doing PLL initialization during boot time in our code(and without loading GEL file) and observed the expected desired timer values.

I did go trough the Timer User Guide, but it doesn't mention how/where the timer module gets the input clock without PLL being initialized. 

Regards

Sud

Sud,

What do you mean by "timer profile values"?

What boot mode are you using when making these measurements?

Please observe the SYSCLKOUT pin under both the uninitialized and initialized cases for the PLL and compare the frequency of SYSCLKOUT with the values you find for the timer. SYSCLKOUT will be running at the same speed as the internal SYSCLK7 signal which is always running at the main clock rate divided by 6.

The C6670 Data Manual shows the clocking architecture in Figure 7-7 "Main PLL and PLL Controller". This shows how SYSCLK7 is generated. The Timer User Guide shows the timer's clock selection logic in Figure 3-1 "Timer Clock Source Block Diagram"; "internal clock" in Figure 3-1 refers to SYSCLK7.

Regards,
RandyP

Hi RandyP,

Its been a long time for now to reply your previous post. The timer problem has haunted back again and I need some help to know the root cause of this timer problem.

By timer profile I mean: Say I have configured the Timer to interrupt every 10 secs and I run the device in real-time (without doing PLL initialization in system init), it is interrupting every 10*8=80 seconds. But, if I run the device after doing the PLL initialization, I get the required timer results (i.e. 10 secs). Whats causing this problem when the timer is used without initializing the PLL 1 (main PLL).

Boot mode is normal JTAG mode. 

And by the way, SYSCLK7 generated by the main PLL is used to clock the Timer module. Question is, if I don't initialize the PLL, from where does the timer module gets its clock source?

Really need some help here right now. Hoping to get this 1-year old puzzle solved. :/

Regards,

Sud

Sud,

If you do not have the device configured the way you expect to use it, it will not run the way you expect it to run. You have to configure the PLL to get the device running at the speed you want before things will run at the speed you want.

As I mentioned in the earlier reply, you can look at SYSCLKOUT to see how fast the device is running.

Or you can run the test application from the Wiki article What is my DSP clock speed. Someone came up with a better way to do this, in a GEL script with the wall clock, but I do not have quick access to that, just this one on the Wiki.

For the clock sources and clock paths, please refer to the data manual for the Main PLL clocking architecture. Something is configured, even if it is the power-on default. Or it is likely that your GEL script configures the PLL in some way. You can look at the PLL registers and fields shown in that Main PLL clocking figure in the data manual to figure out what path is implemented.

But the bottom line is that if you have not configured the clocking architecture to run at the speed that TI-RTOS expects, you cannot expect anything to run at the rate that TI-RTOS thinks it will run. TI-RTOS == SYS/BIOS.

Regards,
RandyP