Help required to decide Multiple DSP booting (6457)...

Akshay,

When each DSP is released from its RESETn signal, each DSP will start trying to read and execute from its EMIF bus. There is nothing inherent to the DSP that will cause it to wait for another DSP to complete its bootload process first.

What does the "MUX inside the FPGA to select the DSP EMIFA data and address lines to select each DSP" actually do? The four DSPs will all be driving their EMIF address and control lines at the same time, so you have not explained anything that can be done to select one or another DSP.

You will need to have some arbitration logic to hold off any DSP that you do not want to have access to the DPRAM at any particular time. Please refer to the EMIF User's Guide for more information on signals to use for bus arbitration.

Regards,
RandyP

HI Randy P,

 Firstly, i will use a De-multiplexer to choose the data and address pins inside the FPGA. After the 1st DSP reads the program, i'l use the select line to choose the nxt DSP. As i tried to understand in depth, i discovered that when EMIF boot mode is selected, the DSP waits at CE3 which has a base address at 0xB0000000. Does this affect the design of my DPRAM?? How does my chip select act for booting through EMIF?? Since EMIF boot is a 8bit asynchronous, can i use the ARDY pin to indicate the DSP to wait till my boot code is ready?? Im sorry if my question are too basic, I have worked on FPGAs but not on DSPs!

Akshay,

Please draw a picture of what you are trying to do. Show the 4 DSPs and the FPGA and the major logic and signal busses.

You are talking about a very complex system that you could be designing different ways. From my side, I do not know anything more to say besides what I have said above, with what I understand of your system at this point.

Regards,
RandyP

The above block diagram gives a simplified approach of what im trying to design.  I have A NAND Flash which contains the program of Processor , FPGA and the DSPs. IN the block diagram above im just representing 2 DSPs so that the design is simpler to understand, but in actual i have four DSPs. The power to Processor, FPGA and DSP is given in parallel, then the Processor is programmed, it programs the FPGA, then it writes the DSP1's program into the DPRAM in FPGA, now the DeMUX selects DSP1  interface to interact with the DPRAM. Now my queries are,

1. During the time taken to program the Processor, the FPGA and writing the DSP1's program into the DPRAM in FPGA, during this time, what will my DSP1 and DSP2 be doing?

2. Will it be waiting at the corresponding location n take the data moment the data is available or can we use the AARDY pin to indicate that the DATA is ready to be read.

3.the datasheet says that it will be waiting at CE3 at 0xB0000000 location, should i consider this when im designing my DPRAM? If yes, den how?

Thank you.

Hi Randy,

Thanks for the reply. It answers 80% of my queries. About the AARDY pin, are u sure i can use it during the boot through EMIF? As i have seen in the timing diagrams, i have never seen the use of AARDY signal for the same. And yes i have considered the use of quadcore / multicore processor, that would be the next version.

Regards

Akshay

Akshay,

You can use AARDY as described in the datasheet and EMIF User Guide to extend any read or write access until AARDY goes to the Ready state.

My concern is whether there is a maximum duration that AARDY can be held off before the EMIF cycle will be aborted. I doubt this is the case, but the only way to find out is if there is a statement to that fact in the datasheet or EMIF User Guide. If there is no statement to this effect, then you are okay.

Regards,
RandyP