McASP/EDMA3 issue

Khan Zubair

On OMAP L138, the McASP and the EDMA3 do not work properly when the number of TDM channels to be transmitted by the McASP are less that the number of slots in the TDM bus. The McASP enters into UNDERRUN error in XSTAT register, causing the output to go to all zeros (auto mute). When the number of transmit channels are equal to the number of slots in the TDM, then things work good, and under run is not received.

Same issue is observed with our own driver, and with the DSP/BIOS driver.

Here is the McASP code that works fine with the EDMA (if you change the XTDM and RTDM registers to 0x00000001 (XMIT/RECV one slot out of two) then it breaks as described above. We are to the point to call it a McASP limitation because we have never seen this issue on the McBSP:

    /*
     * Program mcasp registers.
     * - Use mcasp
     * - Program mcasp as bus master
     * - 32-bits per channel
     * - 2 channels
     * - 32 kHz
     * = 2.048 MHz
     * - TDM
     */

    /*
     * Global Control Register (GBLCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~............. RESVD
     * ...................0............ XFRST     ; RW, 0 = xmt frame sync generator in reset
     * ....................0........... XSMRST    ; RW, 0 = xmt state maching in reset
     * .....................0.......... XSRCLR    ; RW, 0 = xmt serializers in reset
     * ......................0......... XHCLKRST ; RW, 0 = xmt high freq clock in reset
     * .......................0........ XCLKRST   ; RW, 0 = xmt clock divider in reset
     * ........................~~~..... RESVD
     * ...........................0.... RFRST     ; RW, 0 = rcv frame sync generator in reset
     * ............................0... RSMRST    ; RW, 0 = rcv state maching in reset
     * .............................0.. RSRCLR    ; RW, 0 = rcv serializers in reset
     * ..............................0. RHCLKRST ; RW, 0 = rcv high freq clock div in reset
     * ...............................0 RCLKRST   ; RW, 0 = rcv clock divider in reset (pass through)
     */
    _MCASP_Regs_ptr->GBLCTL = 0x00000000;

    /*
     * Receive Format Unit Bit Mask Register (RMASK)
     * 3         2         1
     * 10987654321098765432109876543210
     * 1............................... RMASK31   ; RW, 0 = receive bit
     * .1.............................. RMASK30   ; RW, 0 = receive bit
     * ..1............................. RMASK29   ; RW, 0 = receive bit
     * ...1............................ RMASK28   ; RW, 0 = receive bit
     * ....1........................... RMASK27   ; RW, 0 = receive bit
     * .....1.......................... RMASK26   ; RW, 0 = receive bit
     * ......1......................... RMASK25   ; RW, 0 = receive bit
     * .......1........................ RMASK24   ; RW, 0 = receive bit
     * ........1....................... RMASK23   ; RW, 0 = receive bit
     * .........1...................... RMASK22   ; RW, 0 = receive bit
     * ..........1..................... RMASK21   ; RW, 0 = receive bit
     * ...........1.................... RMASK20   ; RW, 0 = receive bit
     * ............1................... RMASK19   ; RW, 0 = receive bit
     * .............1.................. RMASK18   ; RW, 0 = receive bit
     * ..............1................. RMASK17   ; RW, 0 = receive bit
     * ...............1................ RMASK16   ; RW, 0 = receive bit
     * ................1............... RMASK15   ; RW, 1 = receive bit
     * .................1.............. RMASK14   ; RW, 1 = receive bit
     * ..................1............. RMASK13   ; RW, 1 = receive bit
     * ...................1............ RMASK12   ; RW, 1 = receive bit
     * ....................1........... RMASK11   ; RW, 1 = receive bit
     * .....................1.......... RMASK10   ; RW, 1 = receive bit
     * ......................1......... RMASK9    ; RW, 1 = receive bit
     * .......................1........ RMASK8    ; RW, 1 = receive bit
     * ........................1....... RMASK7    ; RW, 1 = receive bit
     * .........................1...... RMASK6    ; RW, 1 = receive bit
     * ..........................1..... RMASK5    ; RW, 1 = receive bit
     * ...........................1.... RMASK4    ; RW, 1 = receive bit
     * ............................1... RMASK3    ; RW, 1 = receive bit
     * .............................1.. RMASK2    ; RW, 1 = receive bit
     * ..............................1. RMASK1    ; RW, 1 = receive bit
     * ...............................1 RMASK0    ; RW, 1 = receive bit
     */
    _MCASP_Regs_ptr->RMASK = 0xFFFFFFFF;

    /*
     * Receive Bit Stream Format Register (RFMT)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~.................. RESVD
     * ..............00................ RDATDLY   ; RW, 00 = 0-bit delay
     * ................1............... RRVSR     ; RW, 1 = bitstream MSB first
     * .................00............. RPAD      ; RW, 0 = pad extra bits with 0
     * ...................00000........ RPBIT     ; RW, 00000 = no matter when RPAD = 0
     * ........................1111.... RSSZ      ; RW, 1111 = slot size 32 bits
     * ............................0... RBUSEL    ; RW, 0 = use DMA port
     * .............................000 RROT      ; RW, 0 = no rotation
     */
    _MCASP_Regs_ptr->RFMT = 0x000080F0;

    /*
     * Receive Frame Sync Control Register (AFSRCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~................ RESVD
     * ................000000010....... RMOD      ; RW, 000000010 = 2-slot TDM
     * .........................~~..... RESVD
     * ...........................0.... FRWID     ; RW, 0 = frame sync is single bit
     * ............................~~.. RESVD
     * ..............................1. FSRM      ; RW, 0 = internal
     * ...............................0 FSRP      ; RW, 0 = do not invert
     */
      _MCASP_Regs_ptr->AFSRCTL = 0x00000102;

    /*
     * Receive Clock Control Register (ACLKRCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~........ RESVD
     * ........................0....... CLKRP     ; RW, 0 = sample on falling edge of serial clock
     * .........................0...... RESVD
     * ..........................0..... CLKRM     ; RW, 0 = external clock source from ACLKR pin
     * ...........................00011 CLKRDIV   ; RW, divide by 4 to 2.048 MHz
     */
    _MCASP_Regs_ptr->ACLKRCTL = 0x00000003;

    /*
     * Receive High-Frequency Clock Control Register (AHCLKRCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~................ RESVD
     * ................0............... HCLKRM    ; RW, 0 = External clock from AHCLKR pin
     * .................0.............. HCLKRP    ; RW, 0 = not inverted
     * ..................~~............ RESVD
     * ....................000000000000 HCLKRDIV ; RW, 0 = ignore
     */
    _MCASP_Regs_ptr->AHCLKRCTL = 0x00000000;

    /*
     * Receive TDM Time Slot Register (RTDM)
     * 3         2         1
     * 10987654321098765432109876543210
     * 0............................... RTDMS31   ; RW, 0 = rcv tdm time slot 31 inactive
     * .0.............................. RTDMS30   ; RW, 0 = rcv tdm time slot 30 inactive
     * ..0............................. RTDMS29   ; RW, 0 = rcv tdm time slot 29 inactive
     * ...0............................ RTDMS28   ; RW, 0 = rcv tdm time slot 28 inactive
     * ....0........................... RTDMS27   ; RW, 0 = rcv tdm time slot 27 inactive
     * .....0.......................... RTDMS26   ; RW, 0 = rcv tdm time slot 26 inactive
     * ......0......................... RTDMS25   ; RW, 0 = rcv tdm time slot 25 inactive
     * .......0........................ RTDMS24   ; RW, 0 = rcv tdm time slot 24 inactive
     * ........0....................... RTDMS23   ; RW, 0 = rcv tdm time slot 23 inactive
     * .........0...................... RTDMS22   ; RW, 0 = rcv tdm time slot 22 inactive
     * ..........0..................... RTDMS21   ; RW, 0 = rcv tdm time slot 21 inactive
     * ...........0.................... RTDMS20   ; RW, 0 = rcv tdm time slot 20 inactive
     * ............0................... RTDMS19   ; RW, 0 = rcv tdm time slot 19 inactive
     * .............0.................. RTDMS18   ; RW, 0 = rcv tdm time slot 18 inactive
     * ..............0................. RTDMS17   ; RW, 0 = rcv tdm time slot 17 inactive
     * ...............0................ RTDMS16   ; RW, 0 = rcv tdm time slot 16 inactive
     * ................0............... RTDMS15   ; RW, 0 = rcv tdm time slot 15 inactive
     * .................0.............. RTDMS14   ; RW, 0 = rcv tdm time slot 14 inactive
     * ..................0............. RTDMS13   ; RW, 0 = rcv tdm time slot 13 inactive
     * ...................0............ RTDMS12   ; RW, 0 = rcv tdm time slot 12 inactive
     * ....................0........... RTDMS11   ; RW, 0 = rcv tdm time slot 11 inactive
     * .....................0.......... RTDMS10   ; RW, 0 = rcv tdm time slot 10 inactive
     * ......................0......... RTDMS9    ; RW, 0 = rcv tdm time slot 9 inactive
     * .......................0........ RTDMS8    ; RW, 0 = rcv tdm time slot 8 inactive
     * ........................0....... RTDMS7    ; RW, 0 = rcv tdm time slot 7 inactive
     * .........................0...... RTDMS6    ; RW, 0 = rcv tdm time slot 6 inactive
     * ..........................0..... RTDMS5    ; RW, 1 = rcv tdm time slot 5 inactive
     * ...........................0.... RTDMS4    ; RW, 1 = rcv tdm time slot 4 inactive
     * ............................0... RTDMS3    ; RW, 1 = rcv tdm time slot 3 inactive
     * .............................0.. RTDMS2    ; RW, 1 = rcv tdm time slot 2 inactive
     * ..............................1. RTDMS1    ; RW, 1 = rcv tdm time slot 1 ch1
     * ...............................1 RTDMS0    ; RW, 1 = rcv tdm time slot 0 ch0
     */
    _MCASP_Regs_ptr->RTDM = 0x00000003;

    /*
     * Receiver Interrupt Control Register (RINTCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~........ RESVD
     * ........................0....... RSTAFRM   ; RW, 0 = receive start of frame   - interrupt disabled
     * .........................~...... RESVD
     * ..........................0..... RDATA     ; RW, 0 = receive data ready       - interrupt disabled
     * ...........................0.... RLAST     ; RW, 0 = receive last slot        - interrupt disabled
     * ............................0... RDMAERR   ; RW, 0 = receive dma error        - interrupt disabled
     * .............................0.. RCKFAIL   ; RW, 0 = receive clock failure    - interrupt disabled
     * ..............................0. RSYNCERR ; RW, 0 = receive frame sync error - interrupt disabled
     * ...............................0 ROVRN     ; RW, 0 = receive overrun          - interrupt disabled
     */
    _MCASP_Regs_ptr->RINTCTL = 0x00000000;

    /*
     * Receiver Status Register (RSTAT)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~......... RESVD
     * .......................1........ RERR      ; RW, receive logic-or of RVOERN RSYNCERR RCKFAIL RDMAERR
     * ........................1....... RDMAERR   ; RW, receive dma error occurred
     * .........................1...... RSTAFRM   ; RW, receive frame sync detected
     * ..........................1..... RDATA     ; RW, receive data ready
     * ...........................1.... RLAST     ; RW, receive last slot
     * ............................0... RTDMSLOT ; R   even/odd of current timeslot
     * .............................1.. RCKFAIL   ; RW, receive clock failure
     * ..............................1. RSYNCERR ; RW, receive frame sync error
     * ...............................1 ROVRN     ; RW, receive overrun
     */
    _MCASP_Regs_ptr->RSTAT = 0x000001F7;        /* write 1 to clear status */

    /*
     * Receive Clock Check Control Register (RCLKCHK)
     * 3         2         1
     * 10987654321098765432109876543210
     * 00000000........................ RCNT      ; R, receive clock count value
     * ........00000000................ RMAX      ; RW, receive clock max boundary
     * ................00000000........ RMIN      ; RW, receive clock min boundary
     * ........................~~~~.... RESVD
     * ............................0000 RPS       ; RW, 0 = McASP system clock divide by 1
     */
    _MCASP_Regs_ptr->RCLKCHK = 0x00000000;

    /*
     * Transmit Format Unit Bit Mask Register (XMASK)
     * 3         2         1
     * 10987654321098765432109876543210
     * 1............................... XMASK31   ; RW, 0 = transmit bit
     * .1.............................. XMASK30   ; RW, 0 = transmit bit
     * ..1............................. XMASK29   ; RW, 0 = transmit bit
     * ...1............................ XMASK28   ; RW, 0 = transmit bit
     * ....1........................... XMASK27   ; RW, 0 = transmit bit
     * .....1.......................... XMASK26   ; RW, 0 = transmit bit
     * ......1......................... XMASK25   ; RW, 0 = transmit bit
     * .......1........................ XMASK24   ; RW, 0 = transmit bit
     * ........1....................... XMASK23   ; RW, 0 = transmit bit
     * .........1...................... XMASK22   ; RW, 0 = transmit bit
     * ..........1..................... XMASK21   ; RW, 0 = transmit bit
     * ...........1.................... XMASK20   ; RW, 0 = transmit bit
     * ............1................... XMASK19   ; RW, 0 = transmit bit
     * .............1.................. XMASK18   ; RW, 0 = transmit bit
     * ..............1................. XMASK17   ; RW, 0 = transmit bit
     * ...............1................ XMASK16   ; RW, 0 = transmit bit
     * ................1............... XMASK15   ; RW, 1 = transmit bit
     * .................1.............. XMASK14   ; RW, 1 = transmit bit
     * ..................1............. XMASK13   ; RW, 1 = transmit bit
     * ...................1............ XMASK12   ; RW, 1 = transmit bit
     * ....................1........... XMASK11   ; RW, 1 = transmit bit
     * .....................1.......... XMASK10   ; RW, 1 = transmit bit
     * ......................1......... XMASK9    ; RW, 1 = transmit bit
     * .......................1........ XMASK8    ; RW, 1 = transmit bit
     * ........................1....... XMASK7    ; RW, 1 = transmit bit
     * .........................1...... XMASK6    ; RW, 1 = transmit bit
     * ..........................1..... XMASK5    ; RW, 1 = transmit bit
     * ...........................1.... XMASK4    ; RW, 1 = transmit bit
     * ............................1... XMASK3    ; RW, 1 = transmit bit
     * .............................1.. XMASK2    ; RW, 1 = transmit bit
     * ..............................1. XMASK1    ; RW, 1 = transmit bit
     * ...............................1 XMASK0    ; RW, 1 = transmit bit
     */
    _MCASP_Regs_ptr->XMASK = 0xFFFFFFFF;

    /*
     * Transmit Bit Stream Format Register (XFMT)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~.................. RESVD
     * ..............00................ XDATDLY   ; RW, 00 = 0-bit delay
     * ................1............... XRVSR     ; RW, 1 = bitstream MSB first
     * .................00............. XPAD      ; RW, 0 = pad extra bits with 0
     * ...................00000........ XPBIT     ; RW, 00000 = no matter when XPAD = 0
     * ........................1111.... XSSZ      ; RW, 1111 = slot size 32 bits
     * ............................0... XBUSEL    ; RW, 0 = use DMA port
     * .............................000 XROT      ; RW, 0 = no rotation
     */
    _MCASP_Regs_ptr->XFMT = 0x000080F0;

    /*
     * Transmit Frame Sync Control Register (AFSXCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~................ RESVD
     * ................000000010....... XMOD      ; RW, 000000010 = 2-slot TDM
     * .........................~~..... RESVD
     * ...........................0.... FXWID     ; RW, 0 = frame sync is single bit
     * ............................~~.. RESVD
     * ..............................0. FSXM      ; RW, 0 = externally generated frame sync
     * ...............................0 FSXP      ; RW, 0 = do not invert
     */
    _MCASP_Regs_ptr->AFSXCTL = 0x00000100;

    /*
     * Transmit Clock Control Register (ACLKXCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~........ RESVD
     * ........................0....... CLKXP     ; RW, 0 = do not invert
     * .........................1...... ASYNC     ; RW, 1 = tx and rx sections operate separate
     * ..........................0..... CLKXM     ; RW, 0 = external clock source from ACLKX pin
     * ...........................00000 CLKXDIV   ; RW, ignore
     */
    _MCASP_Regs_ptr->ACLKXCTL = 0x00000040;

    /*
     * Transmit High-Frequency Clock Control Register (AHCLKXCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~................ RESVD
     * ............................... HCLKXM     ; RW, 0 = External clock from AHCLKR pin
     * .................0.............. HCLKXP    ; RW, 0 = not inverted
     * ..................~~............ RESVD
     * ....................000000000000 HCLKXDIV ; RW, ignore
     */
    _MCASP_Regs_ptr->AHCLKXCTL = 0x00000000;

    /*
     * Transmit TDM Time Slot Register (RTDM)
     * 3         2         1
     * 10987654321098765432109876543210
     * 0............................... XTDMS31   ; RW, 0 = xmt tdm time slot 31 inactive
     * .0.............................. XTDMS30   ; RW, 0 = xmt tdm time slot 30 inactive
     * ..0............................. XTDMS29   ; RW, 0 = xmt tdm time slot 29 inactive
     * ...0............................ XTDMS28   ; RW, 0 = xmt tdm time slot 28 inactive
     * ....0........................... XTDMS27   ; RW, 0 = xmt tdm time slot 27 inactive
     * .....0.......................... XTDMS26   ; RW, 0 = xmt tdm time slot 26 inactive
     * ......0......................... XTDMS25   ; RW, 0 = xmt tdm time slot 25 inactive
     * .......0........................ XTDMS24   ; RW, 0 = xmt tdm time slot 24 inactive
     * ........0....................... XTDMS23   ; RW, 0 = xmt tdm time slot 23 inactive
     * .........0...................... XTDMS22   ; RW, 0 = xmt tdm time slot 22 inactive
     * ..........0..................... XTDMS21   ; RW, 0 = xmt tdm time slot 21 inactive
     * ...........0.................... XTDMS20   ; RW, 0 = xmt tdm time slot 20 inactive
     * ............0................... XTDMS19   ; RW, 0 = xmt tdm time slot 19 inactive
     * .............0.................. XTDMS18   ; RW, 0 = xmt tdm time slot 18 inactive
     * ..............0................. XTDMS17   ; RW, 0 = xmt tdm time slot 17 inactive
     * ...............0................ XTDMS16   ; RW, 0 = xmt tdm time slot 16 inactive
     * ................0............... XTDMS15   ; RW, 0 = xmt tdm time slot 15 inactive
     * .................0.............. XTDMS14   ; RW, 0 = xmt tdm time slot 14 inactive
     * ..................0............. XTDMS13   ; RW, 0 = xmt tdm time slot 13 inactive
     * ...................0............ XTDMS12   ; RW, 0 = xmt tdm time slot 12 inactive
     * ....................0........... XTDMS11   ; RW, 0 = xmt tdm time slot 11 inactive
     * .....................0.......... XTDMS10   ; RW, 0 = xmt tdm time slot 10 inactive
     * ......................0......... XTDMS9    ; RW, 0 = xmt tdm time slot 9 inactive
     * .......................0........ XTDMS8    ; RW, 0 = xmt tdm time slot 8 inactive
     * ........................0....... XTDMS7    ; RW, 0 = xmt tdm time slot 7 inactive
     * .........................0...... XTDMS6    ; RW, 0 = xmt tdm time slot 6 inactive
     * ..........................0..... XTDMS5    ; RW, 1 = xmt tdm time slot 5 inactive
     * ...........................0.... XTDMS4    ; RW, 1 = xmt tdm time slot 4 inactive
     * ............................0... XTDMS3    ; RW, 1 = xmt tdm time slot 3 inactive
     * .............................0.. XTDMS2    ; RW, 1 = xmt tdm time slot 2 inactive
     * ..............................1. XTDMS1    ; RW, 1 = xmt tdm time slot 1 ch1
     * ...............................1 XTDMS0    ; RW, 1 = xmt tdm time slot 0 ch0
     */
    _MCASP_Regs_ptr->XTDM = 0x00000003;

    /*
     * Transmit Interrupt Control Register (XINTCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~........ RESVD
     * ........................0....... XSTAFRM   ; RW, 0 = transmit start of frame   - interrupt disabled
     * .........................~...... RESVD
     * ..........................0..... XDATA     ; RW, 0 = transmit data ready       - interrupt disabled
     * ...........................0.... XLAST     ; RW, 0 = transmit last slot        - interrupt disabled
     * ............................0... XDMAERR   ; RW, 0 = transmit dma error        - interrupt disabled
     * .............................0.. XCKFAIL   ; RW, 0 = transmit clock failure    - interrupt disabled
     * ..............................0. XSYNCERR ; RW, 0 = transmit frame sync error - interrupt disabled
     * ...............................0 XUNDRN    ; RW, 0 = transmit underrun         - interrupt disabled
     */
    _MCASP_Regs_ptr->XINTCTL = 0x00000000;

    /*
     * Transmit Status Register (XSTAT)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~......... RESVD
     * .......................1........ XERR      ; RW, transmit logic-or of XUNDRN XSYNCERR XCKFAIL XDMAERR
     * ........................1....... XDMAERR   ; RW, transmit dma error occurred
     * .........................1...... XSTAFRM   ; RW, transmit frame sync detected
     * ..........................1..... XDATA     ; RW, transmit data ready
     * ...........................1.... XLAST     ; RW, transmit last slot
     * ............................0... XTDMSLOT ; R   even/odd of current timeslot
     * .............................1.. XCKFAIL   ; RW, transmit clock failure
     * ..............................1. XSYNCERR ; RW, transmit frame sync error
     * ...............................1 XUNDRN    ; RW, transmit underrun
     */
    _MCASP_Regs_ptr->XSTAT = 0x000001F7;          /* write 1 to clear status */

    /*
     * Transmit Clock Check Control Register (XCLKCHK)
     * 3         2         1
     * 10987654321098765432109876543210
     * 00000000........................ XCNT      ; R, transmit clock count value
     * ........00000000................ XMAX      ; RW, transmit clock max boundary
     * ................00000000........ XMIN      ; RW, transmit clock min boundary
     * ........................~~~~.... RESVD
     * ............................0000 XPS       ; RW, 0 = McASP system clock divide by 1
     */
    _MCASP_Regs_ptr->XCLKCHK = 0x00000000;

    /*
     * Serializer Control Register (SRCTL7)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~~~...... RESVD
     * ..........................~..... RRDY      ; R, RBUF contains data
     * ...........................~.... XRDY      ; R, XBUF contains data
     * ............................00.. DISMOD    ; RW, pin is 3-state
     * ..............................10 XPS       ; RW, 02 = serializer is receiver
     */
    _MCASP_Regs_ptr->SRCTL7 = 0x00000002;

    /*
     * Serializer Control Register (SRCTL2)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~~~...... RESVD
     * ..........................~..... RRDY      ; R, RBUF contains data
     * ...........................~.... XRDY      ; R, XBUF contains data
     * ............................00.. DISMOD    ; RW, pin is 3-state
     * ..............................01 XPS       ; RW, 01 = serializer is transmitter
     */
    _MCASP_Regs_ptr->SRCTL2 = 0x00000001;

    /*
     * Pin Direction Register (PDIR)
     * 3         2         1
     * 10987654321098765432109876543210
     * 1............................... AFSR      ; RW, 0 = output
     * .0.............................. AHCLKR    ; RW, 0 = input
     * ..1............................. ACLKR     ; RW, 0 = output
     * ...0............................ AFSX      ; RW, 0 = input
     * ....0........................... AHCLKX    ; RW, 0 = input
     * .....0.......................... ACLKX     ; RW, 0 = input
     * ......0......................... AMUTE     ; RW, 0 = input
     * .......~~~~~~~~~................ RESVD
     * ................0............... AXR15     ; RW, 0 = input
     * .................0.............. AXR14     ; RW, 0 = input
     * ..................0............. AXR13     ; RW, 0 = input
     * ...................0............ AXR12     ; RW, 0 = input
     * ....................0........... AXR11     ; RW, 0 = input
     * .....................0.......... AXR10     ; RW, 0 = input
     * ......................0......... AXR9      ; RW, 0 = input
     * .......................0........ AXR8      ; RW, 0 = input
     * ........................0....... AXR7      ; RW, 0 = input
     * .........................0...... AXR6      ; RW, 0 = input
     * ..........................0..... AXR5      ; RW, 0 = input
     * ...........................0.... AXR4      ; RW, 0 = input
     * ............................0... AXR3      ; RW, 0 = input
     * .............................1.. AXR2      ; RW, 0 = output
     * ..............................0. AXR1      ; RW, 0 = input
     * ...............................0 AXR0      ; RW, 0 = input
     */
    _MCASP_Regs_ptr->PDIR = 0xA0000004;

    /*
     * Digital Loopback Control Register (DLBCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~.... RESVD
     * ............................00.. MODE      ; RW, 00 = default when disabled
     * ..............................0. ORD       ; RW, 0 = when enabled odd serilizer N+1 Tx to even serializer N Rx
     * ...............................0 DLBRN     ; RW, 0 = loopback disabled
     */
    _MCASP_Regs_ptr->DLBCTL = 0x00000000;

}

    /*
     * Global Control Register (GBLCTL)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~~~~~~~~~~~~............. RESVD
     * ...................1............ XFRST     ; RW, 1 = xmt frame sync generator active
     * ....................1........... XSMRST    ; RW, 1 = xmt state maching running
     * .....................1.......... XSRCLR    ; RW, 1 = xmt serializers active
     * ......................1......... XHCLKRST ; RW, 1 = xmt high freq clock div running
     * .......................1........ XCLKRST   ; RW, 1 = xmt clock divider running
     * ........................~~~..... RESVD
     * ...........................1.... RFRST     ; RW, 1 = rcv frame sync generator active
     * ............................1... RSMRST    ; RW, 1 = rcv state maching running
     * .............................1.. RSRCLR    ; RW, 1 = rcv serializers active
     * ..............................1. RHCLKRST ; RW, 1 = rcv high freq clock div running
     * ...............................1 RCLKRST   ; RW, 0 = rcv clock divider running
     */

    /*
     * Start the high frequency serial clocks
     */

    _MCASP_Regs_ptr->GBLCTL |= (1 << 9);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 9)) == 0 ){
        _MCASP_sleep(1);
    }

    _MCASP_Regs_ptr->GBLCTL |= (1 << 1);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 1)) == 0 ){
        _MCASP_sleep(1);
    }

    /*
     * Start the serial clocks
     */

    _MCASP_Regs_ptr->GBLCTL |= (1 << 8);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 8)) == 0 ){
        _MCASP_sleep(1);
    }

    _MCASP_Regs_ptr->GBLCTL |= (1 << 0);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 0)) == 0 ){
        _MCASP_sleep(1);
    }

    /*
     * Clear all status error bits.
     */

    _MCASP_Regs_ptr->XSTAT = 0x0000FFFF;
    _MCASP_Regs_ptr->RSTAT = 0x0000FFFF;

    /*
     * Start the serializers
     */

    _MCASP_Regs_ptr->GBLCTL |= (1 << 10);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 10)) == 0 ){
        _MCASP_sleep(1);
    }

    _MCASP_Regs_ptr->GBLCTL |= (1 << 2);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 2)) == 0 ){
        _MCASP_sleep(1);
    }

    /*
     * Start the state machines
     */

    _MCASP_Regs_ptr->GBLCTL |= (1 << 11);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 11)) == 0 ){
        _MCASP_sleep(1);
    }

    _MCASP_Regs_ptr->GBLCTL |= (1 << 3);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 3)) == 0 ){
        _MCASP_sleep(1);
    }

    /*
     * Start the frame sync generators
     */

    _MCASP_Regs_ptr->GBLCTL |= (1 << 12);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 12)) == 0 ){
        _MCASP_sleep(1);
    }

    _MCASP_Regs_ptr->GBLCTL |= (1 << 4);
    while( (_MCASP_Regs_ptr->GBLCTL & (1 << 4)) == 0 ){
        _MCASP_sleep(1);
    }

over 12 years ago

0 Sunil Kamath over 12 years ago

TI__Expert 7470 points

Zubair,

As you are using the DMA port to write to and read from the McASP XRBUF registers, you will have to service all active TX or RX serializers in the appropriate DMA event. This is documented in section 25.2.4.3.2 Transfers through the DMA Port in the TRM (spruh77a.pdf).

If you choose to use the peripheral configuration port to write to individual XBUF/RBUF registers, this is not necessary.

Regards,

Sunil

0 Elron A Yellin over 12 years ago in reply to Sunil Kamath

Expert 1040 points

Sunil,

I believe that I am servicing all active serializers, but I'm having the same problem as Zubair.

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/246981.aspx

If TI could produce sample code that demonstrates the use of disabled TDM slots read/written through the DMA port, I think that would settle everything.

Thanks,

Elron

0 Khan Zubair over 12 years ago in reply to Elron A Yellin

Prodigy 90 points

Sunil

I am servicing all active serializers. I only have one active TX and one active RX serlizer.

I also captured on logic analyzer and it seems that after reset, the McASP does transmit 5 to 20 samples (in correct slots), then underrun occurs, and underrun as documented, causes a mute on the serializer output. You cannot get out of mute until you reset the McASP (documented by TI). So I reset the McASP, and same thing happens over again.

Interestingly, the DMA keeps servicing the serializer and timing seems correct. That is 32000 samples get transferred every second on 32kHz FS. But the McASP insists on sending zeros to the output due to underrun. Again, this happens only when selective channels/slots are used in the frame.

Clearing the underrun bit has no effect in XSTAT, and output.

Zubair

0 Khan Zubair over 12 years ago in reply to Khan Zubair

Prodigy 90 points

Anyone can provide explanation on this OMAP problem?

0 Sivaraj Kuppuraj over 12 years ago in reply to Khan Zubair

TI__Mastermind 35645 points

Hi Zubair,

Thanks for your post again.

In order to recover from Underrun Error, resetting McASP and restarting again with proper initialization will usually help. But in your case, you mention that, you have tried this. If any clock failure happens, then resetting McASP and restarting again will not be effective until after a clock failure check start up procedure is undertaken. Please refer Section 25.2.4.7.6.1 Clock-Failure Check Startup procedure mentioned in spruh77a.pdf document. Please check for any transmit clock failure by doing the start up procedure and ensure the transmit clock falls within the acceptable range. Then, Please try resetting the McASP & DMA and reinitialize both.

Please check the link below for spruh77a.pdf document:

http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

I hope, this should fix the Underrun Error.

Please let us know your update on the same.

Thanks & regards,

Sivaraj K

---------------------------------------------------------------------------------
Please click the Verify Answer button on this post if it answers your question.
---------------------------------------------------------------------------------

0 Elron A Yellin over 12 years ago in reply to Sivaraj Kuppuraj

Expert 1040 points

I think the actual question is not how to recover from underrun, but why the underrun is happening. Can you provide sample code that actually works with some inactive TDM slots?

Elron

0 Sivaraj Kuppuraj over 12 years ago in reply to Elron A Yellin

TI__Mastermind 35645 points

Hi Elron,

Thanks for your post.

Underrun is happening because, when the transmit serializer is instructed to transfer data from XBUF to XRSR, but XBUF has not yet been serviced with new data since the last transfer.

We don't have any sample code to work with inactive TDM slots.

Thanks & regards,

Sivaraj K

------------------------------------------------------------------------------------------------
Please click the Verify Answer button on this post if it answers your question.
------------------------------------------------------------------------------------------------

0 Elron A Yellin over 12 years ago in reply to Sivaraj Kuppuraj

Expert 1040 points

Sivaraj Kuppuraj said:

Underrun is happening because, when the transmit serializer is instructed to transfer data from XBUF to XRSR, but XBUF has not yet been serviced with new data since the last transfer.

Yes, that is what underrun means, the question is why is it happening?

The MCASP works with all slots active. Deactivating N slots and reducing the DMA BCNT by N doesn't work.

We don't have any sample code to work with inactive TDM slots.

Can someone verify that inactive TDM slots actually work on the L138?

Thanks,

Elron

0 Khan Zubair over 12 years ago in reply to Elron A Yellin

Prodigy 90 points

As suggested, I enabled clock check, and made sure, I do not start the DMA, and the McASP frame sync generation, before enough time has elapsed to permanently clear the clock check error bit in the XSTAT register. The clock check error bit can be cleared till next reset after proper XCLKCHK setup. However, no change in behavior of this issue. McASP keeps in under run, and even after reset of both McASP and the DMA, enters under run again. Point taken, clocks are stable.

I think I have stated previously that the under run is not immediate. It occurs, after a few samples have been transmitted. This means that the McASP can transmit in selective slots, only that it is not just very friendly with the DMA when selective slots are used.

I can give you my code if you give me an email address. So you can try yourself.

I added the following code:

    /*
     * Start the McASP state machines in GBL register
     */

...

    /*
     * Setup the Xmit clock check register
     */

    /*
     * Transmit check clock control register (XCLKCHK)
     * 3         2         1
     * 10987654321098765432109876543210
     * ~~~~~~~~........................ XCNT      ; RO
     * ........00010100................ XMAX      ; RW, 20 = max clock range
     * ................00010000........ XIN       ; RW, 16 = min clock range
     * ........................~~~~.... RESVD     ;
     * ............................0101 XPS       ; RW, prescale by 32
     */
    _MCASP_Regs_ptr->XCLKCHK = 0x00141005;

    /*
     * Wait for clock errors to disappear.
     */
    while(_MCASP_Regs_ptr->XSTAT & 4) {
        _MCASP_sleep(100);
        _MCASP_Regs_ptr->XSTAT = _MCASP_Regs_ptr->XSTAT;
    }

    /*
     * Start the frame sync generators in GBL register, and DMA to start servicing samples
     */

0 George Hanna over 11 years ago in reply to Khan Zubair

Prodigy 20 points

Hi Zubair,

I am wondering if you found a resolution for this? I am experiencing the same issue. By the way, what voltage are you powering the Freon with? I found that this problem only exists at around 1 volt.

George

0 Khan Zubair over 11 years ago in reply to George Hanna

Prodigy 90 points

Hi George

Yes, we found a solution. We changed the hardware :)

Zubair

0 George Hanna over 11 years ago in reply to Khan Zubair

Prodigy 20 points

Hi Zubair,

That's good news! :) Would you be able to give a general explanation of what changed in the hardware? Are you still deactivating any of the slots in the frame?

Thanks,

George

0 Khan Zubair over 11 years ago in reply to George Hanna

Prodigy 90 points

We changed the HW so that each DSP gets only the channels it needs to process, at the clock rate that fits those channels completely with no empty slots.

Hence no multi-channel operation on McASP. We know that the OMAP L138 on McASP cannot do multi channel operation with the EMDA. If we do more designs with this chip, we will not use McASP for multi channel.

Zubair

0 Tufino over 11 years ago in reply to Khan Zubair

TI__Intellectual 2350 points

Zubair,

Actually, the McASP on that device has been used in many products over the last several years to provide multichannel audio, very often using EDMA. McASP was developed specifically for multichannel audio.

If you feel that I've misunderstood your assertion, would you please clarify?

Thanks,
Bobby

0 Elron A Yellin over 11 years ago in reply to Tufino

Expert 1040 points

Bobby,

The problem Zubair and I have been asking about is that McASP/EDMA doesn't seem to work with inactive TDM slots. There is no TI sample code that demonstrates it working, and in nine months, no one has proposed anything that we might be doing wrong.

Elron

0 Tufino over 11 years ago in reply to Elron A Yellin

TI__Intellectual 2350 points

Elron,

Understood. I was responding specifically to the statement that McASP doesn't support multichannel with EDMA.

Unfortunately, I do not have any example code to share. Internally, we ran validation programs setting, for instance, all even slots active and odd slots inactive, and vice versa, and verified that the feature works. I have not been involved with this thread until very recently, so I can't venture a guess as to what could be going wrong in your particular case. But the feature was definitely proven out before we went to production with the device.

Bobby

0 Khan Zubair over 11 years ago in reply to Tufino

Prodigy 90 points

Bobby

McASP works with multichannel with EDMA fine. If you read the entire thread, I stated many times, and even in my last email that the problem occurs when there is at least one inactive slot on the TDM. The McASP cannot handle that slot properly, and hangs the EDMA by going into underrun.

Honestly, you have made the DMA quite complicated (since C5x). So you should provide working example code.

Zubair

0 Sivaraj Kuppuraj over 11 years ago in reply to Khan Zubair

TI__Mastermind 35645 points

Hi Zubair,

Could you please share your code, sothat, i shall try to reproduce this at my end?

my email address: sivaraj.k@ti.com

Thanks & regards,

Sivaraj K

0 Khan Zubair over 11 years ago in reply to Sivaraj Kuppuraj

Prodigy 90 points

Hi Sivaraj,

Sent the code to the provided email. By the way, as I mentioned, we changed the HW so now we have no empty slot in the TDM. You will need to add an empty slot to reproduce the problem. The code at the top of this post shows adding an empty slot.

Regards

Zubair

0 Sivaraj Kuppuraj over 11 years ago in reply to Khan Zubair

TI__Mastermind 35645 points

Hi Zubair,

Thanks for sending the driver code.

By the way, in which platform you have experimented , I mean, you have used logicPD EVM or experimenter kit or any other?

So that, i shall try using the same one.

Thanks & regards,

Sivaraj K

0 Khan Zubair over 11 years ago in reply to Sivaraj Kuppuraj

Prodigy 90 points

Hi Sivaraj

This driver wont work on EVM.

But I can send you a board we made if you like. Runs linux and everything is in place to run the driver on the DSP through DSPLINK.

Zubair

0 Mukul Bhatnagar over 11 years ago in reply to Khan Zubair

TI__Guru* 83855 points

Zubair, Elron

This issue was further debugged and root caused to a device issue.

An upcoming version of the errata will have the following usage note

McASP: Inactive Slot Usage Note

On all silicon revisions, in any McASP serializer configured a transmit serializer with an n-slot TDM, data transfer can fail if both of the conditions below are true:

1. one or more time slots within the n-slot TDM are configured as inactive and

2. EDMA is used to transfer data to McASP

If the conditions mentioned above exists, either the transmit operation may fail to start with the XDATA bit in the Transmit Status Register (XSTAT) set or if the transmit operation has started, random underrun errors may occur breaking the data transfer operation. To ensure correct McASP transmit operation with EDMA triggered data transfers, all time slots in an n-slot TDM should be configured as active slots. For example, if a serializer is configured for transmit operation with a 5-slot TDM frame in which it is only required to transmit data in slots 0 to 2, all five slots (0 to 4) should be configured as active in the Transmit TDM Time Slot Register (XTDM). In this example the remaining time slots (slot 5 onwards) can be configured as inactive. The EDMA configuration and user application should account for the transfer of extra data to the McASP for slots 3 and 4.

Processors

Processors forum

McASP/EDMA3 issue