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Dummy cycles requirement in Quad read mode of N25Q032A SPI flash

Prashant Gawade
Prodigy 10 points

Hello Friends,

I have N25Q032 flash connected to TI DSP. I have a questions related to requirement of dummy cycles with respect to different opcodes modes of N25Q032 flash. 
I wanted to communicate with it at 100MHz with less overhead. Therefore I will be using Quad mode of operation (command, address and data on all four lines) i.e. Quad SPI Protocol.
Looking at table-13 'Supported clock frequencies':
If I use Quad I/O FAST read (0xEB) mode, then I need to use 9 dummy cycles.
But If I use FAST Read (0x0B) mode, then looks like I may need only 3 dummy cycles.
So, my question is if the protocol in both modes is same (command, ADDR and data on DQ[3:0]), why there is difference in dummy cycles when using these two modes? How SPI behaves differently in these two modes, which has same timings?

Thanks,
PG