• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 100 subscribers
  • Views 325 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Unexpected L1D cache size

Remco Poelstra
Intellectual 985 points

Other Parts Discussed in Thread: OMAP-L138

Hi,

 

I've an C6748 on a C6748LCDK.

The datasheet states that I've 32kB of L1D cache.

It should boot either with 32kB cache or 0kB cache. I couldn't find which one it is for this chip, but the cache browser as well as the memory browser at address 0x01840 0040 shows that the cache is configured as 16kB.

How is that possible? The GEL file does not seem to configure the cache, nor does my (starterware) user program.

Regards,

 

Remco Poelstra

  • 0
    TI__Expert 4760 points

    Hi Remco,

    We do get the same value if we put the OMAP-L138 in neither UART2, NOR or NAND Boot mode. If we change it

    to Emulation or SPI boot mode we don't get this it defaults to 7h (32Kb L1D)

    The internal ROM initializes these values upon power up.

    Thanks for pointing it out.

    • --------------------------------------------------------------------------------------------------------
      Please click the Verify Answer button on this post if it answers your question.
      --------------------------------------------------------------------------------------------------------

    Regards

    Antony

  • 0 in reply to Antony Samsunil
    TI__Expert 7470 points

    Remco,

    As Antony has suggested, the internal ROM bootloader changes the L1D cache size from 32KB to 16KB during the boot process. In the event of a successful boot process (from any chosen boot mode), the bootloader restores the L1D cache value to the default value (32KB) before handing over control to the user code. But, when the boot process is not successful (as with the UART2 boot mode on the LCDK), the L1D cache value remains at 16KB.

    Regards,

    Sunil

  • 0 in reply to Sunil Kamath
    Intellectual 985 points

    Thanks for the replies.

    I suppose it's ok to just configure the cache otherwise in user code?

    I use uart boot to make sure that the code in nand is not loaded and then use ccs to load my own code.

    Regards,

    Remco Poelstra

  • 0 in reply to Remco Poelstra
    TI__Expert 7470 points

    Remco,

    Yes, you can configure cache in user code.

    Regards,

    Sunil