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[DM8148] linux-omap3 SATA PLL config changeset breaks ethernet?

Jon S.
Expert 1240 points

Hi all,

A while back I had worked on bringing up a DM8148-based board up to date with linux-omap3 master in order to get UBIFS + BCH16 up and running.

In doing so, I found that some changest broke Ethernet (RGMII) functionality for the DM8148 -- the device began failing to send packets over ~600 bytes.

I tracked the issue down to commit 135128bdbebb86f7a69554b99de596a22531affb, in which the configuration of the SATA PLL registers was changed to switch from a 20 MHz clock to a 100 MHz clock.

Since we're not using SATA in our application, a simple workaround is to remove the call to ti814x_sata_pllcfg() in from omap2_init_devices() (device.c).

However, I just wanted to ask whether anyone else ran across this. Is this a defect, or would one need to make some other changes if they wanted to use both SATA and RGMII?

For reference, the relevant sections of the DM8148 TRM (SPRUGZ8B, Nov 12 2011 revision) that I'm reviewing to obtain a better understanding of the SATA/EMAC clock structure are:

  • Section 9.1.5 (EMAC) Interface Clokcing
  • Figure 9-2, 3PSW Subsystem Clocking Block Diagram
  • Section 21.5, "SATA PLL Registers"
  • Figure 2-6, "Clock Structure"
  • Figure 2-10, "SERDES and Ethernet Clock Structure"
  • 0
    TI__Expert 8250 points

    Hi

    SATA Serdes feeds 50Mhz and 125Mhz clock inputs to the EMAC module. The above patch reprograms the SATA SERDES module to generate the clock based on 100Mhz differential clock input instead of the 20Mhz Osc source. This has been validated on the DM8148 EVM- the above mentioned patch is required to guarantee stable SATA operation and assumes that you have 100Mhz Differential source on your Board.

    If 100Mhz differential source is not populated it would not work(you can cross check for this on your platform).

     In your case, you could revert the patch if SATA functionality is not required

    Regards

    Sriram

  • 0 in reply to Srirama Govindarajan
    Expert 1240 points

    Hi Sriram,

    Thanks so much for the detailed and quick response. I'll look into whether that SERDES xref clock is (a) populated and (b) operating correctly.

    Best regards,

    Jon

  • 0 in reply to Srirama Govindarajan
    Expert 1240 points

    Hi there,

    Sorry, I jumped the gun on marking this verified.  I found that we do indeed have the 100 MHz differential clock source on our boards, and measured that its frequency is correct, so I'm still wondering why this changeset negatively impacts our Ethernet functionality on our custom boards.

    Based upon the attached diagram, I see that I should be able to route the 50MHz output of the SATA SERDES block to the "rmii_refclk" pin (PINCNTL 232, J37) in order to verify that the source to the [/10] --> [RGMII 5MHz ref] section is getting supplied with the correct frequency. 

    Furthermore, DM8148 TRM Figure 9-2 ("3PSW Subsystem Clocking Block Diagram) states that "rmii_refclk I or O depends on PINMUX232".  However, the datasheet states that PINCTL232 (J7) = 0x1 is EMAC_RMREFCLK, but does not account for I vs O.  I see that associated registers allow the RGMII source to be changed, but don't see anything about driving the refclk with the 50 MHz signal.  Is it possible to route the 50MHz (yellow in below diagram) to the pin J27 as an output?

    Any advice on further investigating this?

    As you mentioned, this has been verified on the DM8148 EVM which we have -- perhaps there's a few signals I could compare between our HW and the EVM?

    Thanks,

    Jon