Problem with Configuring AIC3204

Shyam

Expert 1960 points

Hi
im using aic3204 on a ezDSP C5515 based design board,in the event of trying to capture audio from the codec and feeding that pcm data to speex open source codec

i doubt the codec configurations done i use a electret (2 wired ) micro phone usually it requires mic bias and im using to LDO for that purpose my configuration code as follows

/* ------------------------------------------------------------------------ *

* Configure AIC3204 *
* Set of Values: NADC=10;MADC=3;AOSR=128;R=2;P=1;J=1;D=28; *
* PLL_CLKIN =12Mhz *
* CODEC_CLKIN = PLL CLK=30720000 *
* CODEC_CLKIN = NADC * MADC * AOSR * ADCFS =10*3*128*8000 *
* PLL_CLK = PLL_CLKIN * R * J.D / P = 12000000*2*1.28/1=3072000 *
* PLL_CLKIN = MCLK = 12MHz *
* ADCFS = 8KHz *
* ------------------------------------------------------------------------ */

//1.Software Reset
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_wait_Test( 200 ); // Wait
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power

// 2.PLL and Clocks Dividers configuration and Power Up For 8KHz Sampling Rate
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 1 ); // PLL setting: J = 1
AIC3204_rset( 7, 0x00 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x1c ); // PLL setting: LO_BYTE(D)
//AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x12 ); // PLL setting: Power up PLL, P=1 and R=2
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
AIC3204_rset( 18, 0x8A ); // Power up NADC and set NADC value to 10
AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

//3.Processing Blocks Configuration
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset(61,5); //Select PRB_R5

//4.ADC ROUTING and Power Up

AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset(10,0x43); //common mode control register
AIC3204_rset(51,0x68); //MicBias = LDO_IN
AIC3204_rset( 55, 0xc0 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 0x5f ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0x5f ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC

AIC3204_rset( 0, 0x00 );

*/
USBSTK5515_wait_Test( 200 ); // Wait
prints("\rCodec Initialization done \n");
/* I2S settings */
I2S2_SRGR = 0x0015;
I2S2_ICMR = 0x0028; // Enable interrupts
I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C
prints("\rI2S Initialization done\n");

Even the Configuration seems OK i am not able to take any valid input data from the codec,if i want to check the loop back how could i do for this configuration, Kindly please resolve my problem

over 12 years ago

0 Mark M over 12 years ago

TI__Mastermind 30240 points

Hi Shyam,

Looks like you are configuring the Codec to be I2S master at the same time as configuring the DSP to be I2S master.

AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence

...conflicts with...

I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C

Probe the I2S BCLK and WCLK - they should show contention.

Serializer is configured as a master. I2Sn_CLK and I2Sn_FS pins are configured as outputs and
driven by the clock generators. The bit-clock and frame-synchronization signals are derived from
the internal CPU clock.

Where does the MIC_BIAS go on the schematics? The MIC bias needs to supply the electret microphone through a resistor (2.2k) to the signal line.

Hope this helps,
Mark

0 Shyam over 12 years ago in reply to Mark M

Expert 1960 points

Mark Mckeown said:

Looks like you are configuring the Codec to be I2S master at the same time as configuring the DSP to be I2S master.

AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence

...conflicts with...

I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C

Probe the I2S BCLK and WCLK - they should show contention.

Serializer is configured as a master. I2Sn_CLK and I2Sn_FS pins are configured as outputs and
driven by the clock generators. The bit-clock and frame-synchronization signals are derived from
the internal CPU clock.

Where does the MIC_BIAS go on the schematics? The MIC bias needs to supply the electret microphone through a resistor (2.2k) to the signal line.

Thanks for you immediate concern Mr.Mark

yeah i have changed the settings of the code slightly and i have provided the external mic bias resistance and they are below but still its not able to capture valid samples

// Configure AIC3204
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_wait_Test( 200 ); // Wait
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 0, 0 ); // Select page 0
// PLL and Clocks config and Power Up
AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 4 ); // PLL setting: J = 4
AIC3204_rset( 7, 0x17 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0xc0 ); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0xA4 ); // PLL setting: Power up PLL, P=2 and R=4
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR)
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR)
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
AIC3204_rset( 11, 0x80+36 ); // Power up NDAC and set NDAC value to 36
AIC3204_rset( 12, 0x83 ); // Power up MDAC and set MDAC value to 3
AIC3204_rset( 18, 0x80+36 ); // Power up NADC and set NADC value to 36
AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

// DAC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 6 ); // Unmute HPL , 6dB gain
AIC3204_rset( 17, 6 ); // Unmute HPR , 6dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait_Test( 500 ); // Wait
// ADC ROUTING and Power Up
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset(10,0x43); //common mode control register
AIC3204_rset(51,0x68); //MicBias = LDO_IN

AIC3204_rset( 52, 0x30 ); // IN1_L Routed to Left PGA - For new AED board (03) Left +
AIC3204_rset( 54, 0xC0 ); // CM_1 (common mode) to LADC_M through 40 kohm Left -
AIC3204_rset( 59, 80 ); // MIC_PGA_L unmute Left Mic PGA = 40 dB

AIC3204_rset( 81, 0x80 ); // Powerup Left
AIC3204_rset( 82, 0x08 ); // Unmute Left and Mute Right

please i need your comments by the way i have installed the software AIC3204 CS ,wont i be able to access the software if i dont have the EVM ?

is there any other way to fastly configure the AIC3204 TI engineers must look at this issue

0 Shawn Steenhagen over 12 years ago in reply to Shyam

Expert 1535 points

Are you doing this software work on the 5515 ezdsp or your own hardware design? I would suggest working out all the software issues on the 5515 ezdsp first (i.e. use that hardware platform to get the i/o working @ 8Khz mono, with AIC as Master) and then try it on your new hardware to rule out HW issues. I suspect there may be issues with the I2S settings. Look at some of the examples provided with v3.0x of the Chip Support Library.

0 Shyam over 12 years ago in reply to Shawn Steenhagen

Expert 1960 points

yeah i respect your suggestions

i still need more suggestions

my programs flow

1.Take pcm data from aic3204(what diff it will be if i config as master or slave ?)

2.read the data through i2s interface as shown in ezDSp c5515

3.send that 16bit sample to the codec( iam using speex)

4.get the compressed data and send it through UART

targets 2,3,4 are any ways coded well and checked

thing remained is achievement 1 .....now i want to start it very clear the configuration manual clearly says

step1:software reset done any ways

AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_wait_Test( 200 ); // Wait
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power

step2:clock and pll settings for 8Khz signal

AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 4 ); // PLL setting: J = 4
AIC3204_rset( 7, 0x17 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0xc0 ); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0xA4 ); // PLL setting: Power up PLL, P=2 and R=4
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR)
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR)
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
AIC3204_rset( 11, 0x80+36 ); // Power up NDAC and set NDAC value to 36
AIC3204_rset( 12, 0x83 ); // Power up MDAC and set MDAC value to 3
AIC3204_rset( 18, 0x80+36 ); // Power up NADC and set NADC value to 36
AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

step3:confiuring processing blocks by default it is A so there is not need for me to set it

in my case i want to configure for both loop back testing and also capture(it can happen ?)

step4:ADC routing and power up

AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset(10,0x43); //common mode control register
AIC3204_rset(51,0x68); //MicBias = LDO_IN

AIC3204_rset( 0, 0 ); // Select page 0

AIC3204_rset( 81, 0x80 ); // Powerup Left
AIC3204_rset( 82, 0x08 ); // Unmute Left and Mute Right

step 5:DAC routing and power up

AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 6 ); // Unmute HPL , 6dB gain
AIC3204_rset( 17, 6 ); // Unmute HPR , 6dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0

i have choose to listen the audio from right left and my mic in also comes from line 2 left so i have unmuted left and muted right

next i have to configure my I2S where c55 must be configured as slave to listen to aic3204

Slave settings:

I2S2_SRGR = 0x0015;
I2S2_ICMR = 0x0028; // Enable interrupts
I2S2_CR = 0x8010; // 16-bit word, Slave, enable I2C

Now i am able to get a valid data from MSW of Left channel data register is that desired? shouldn't it come from left channel LSW,

Real Problem is with speex is there any TI engineer who worked on speex who could help me

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Problem with Configuring AIC3204