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Run application from NAND flash evm6678

sulvan
Prodigy 70 points

Hi everybody,

I'm using EVM6678, mcsdk_2_01_02_06 and ccs_5.2.1.00018. I have tried simple Hello World example application. This application send throw UART Hello world and this work fine with JTAG debugger, but i can´t get to work from NAND memory, COM-Port terminal program gets following:

IBL: PLL and DDR Initialization Complete
IBL Result code 00
IBL: Booting from NAND
IBL: Booting from NAND
IBL: Booting from NAND
IBL: Booting from NAND

..... - many times....

My steps were:

Dip switches: SW3 (off, on, on, on), SW4 (on, on, on, on), SW5(on, on, on, off) - I2C in Master mode ! And SW6 (on, on, on, on).

1. I program i2crom_0x51_c6678_le.bin from \tools\boot_loader\ibl\src\make\bin\ to the EEPROM at I2C BUS address 0x51 using EEPROM Writer CCS project following README.txt from the EEPROM writer project. In the eepromwriter_input.txt file I type:

file_name  = app.bin           /* i2crom_0x51_c6678_le.bin was renamed to app.bin
bus_addr   = 0x51
start_addr = 0
swap_data  = 0

At the end I get message: "EEPROM programming completed successfully"

2. In setConfig_c66xx_main() of tools\boot_loader\ibl\src\make\bin\i2cConfig.gel, I replaced
          ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_BBLOB;
      with
          ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_ELF;

3. I re-programed the boot configuration table folowing instructions from evmc6678-instructions.txt taken from mcsdk_2_01_02_06

a) I run i2cparam_0x51_c6678_le_0x500.out program from \tools\boot_loader\ibl\src\make\bin.

b) Then I loaded corrected (see p.2 above) GEL-file i2cConfig.gel and run script "EVM c6678 IBL -> setConfig_c6678_main".

c) After press "ENTER" in CCS console the program wrote boot parameter table to EEPROM, and I saw the message "I2c table write complete".

4. After that I programmed my simple application to NAND using nandwriter project from \tools\writer\nand\evmc6678l following README.txt file in the project:

a) File nandwriter_input.txt was used with default parameters.

b) Program writer\nand\evmc66xxl\bin\nandwriter_evm66xxl.out was loaded to CCS.

c) I loaded my app.out (I had problem convert it to the app.bin. I have tried rename app.out to the app.bin with same result) to memory from address 0x80000000. Type-size was selected as 32-bits.

d) Then nandwriter program was started and binary data was written to NAND flash. At the end I saw message "NAND programming completed successfully" in CCS console.

Then I set dip sweetchers: SW3 (off, off, on, off), SW4 (on, off, on, on), SW5 (on, on, on, off) and SW6 (on, on, on, on).

All steps are OK, but my application does not work from NAND after restart EVM6678 board. Anyone can tell my where is my error ?

I have used post by

  • 0
    TI__Guru* 95265 points

    Petr,

    My steps were:

    Dip switches: SW3 (off, on, on, on), SW4 (on, on, on, on), SW5(on, on, on, off) - I2C in Master mode ! And SW6 (on, on, on, on).

    When use the eeprom writer and nand writer to program, please set the EVM to no-boot mode: SW3 (off, on, on, on), SW4 (on, on, on, on), SW5(on, on, on, on) and SW6 (on, on, on, on). This makes sure the GEL script runs to intialize the DDR3 memory. In your step 4 c), you loaded app.out to DDR3 0x80000000. I think the DDR3 was not initialized and garbage was written to NAND.

    Regards, Eric 

  • 0 in reply to lding
    Prodigy 70 points

    Hi,

    i have set Dip switches to no-boot mode, as you wrote with same result. Sorry, i did everything, what is written in the readme.txt in directory eeprom, nand and i can´t use my simple UART program after booting. Later, i will need boot multicore application using MAD.

    Sincerely,

    Petr Kriz

  • 0 in reply to sulvan
    TI__Guru* 95265 points

    Petr,

    Did NAND boot work for you if you still use BBLOB format and convert the .out file into a .bin file and program the .bin file to NAND?

    Regards, Eric

  • 0 in reply to lding
    Prodigy 70 points

    Hi Eric,

    i have changed ibl_BOOT_FORMAT_BBLOB in i2cConfig.gel to ibl_BOOT_FORMAT_ELF. I have tried load program in *.bin file, it had smaller size than *.out file. I used this command " tiobj2bin.bat  app.out  app.bin  ofd6x.exe  hex6x.exe  mkhex4bin.exe". Is this correct? It still doesn´t work. On the forum is many advice, but nothing works for me. Please, could you send me manual, how i should proceed to get it work? Thank you.

    Sincerely,

    Petr Kriz

  • 0 in reply to sulvan
    TI__Guru* 95265 points

    Petr,

    I tested the following way and NAND boot is working as expected:

    1) mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util\iblConfig\src\device.c, edit this file by changing ibl_t c6678_ibl_config(void) ====> if you are using 6678.   
      ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_ELF;

    Re-build IBL.

    2) Set card to no-boot mode, use EEPROM writer to write ibl.bin into 0x51. Rememebr the address is 0x0c000000.

     

    [C66xx_0] EEPROM Writer Utility Version 01.00.00.05

    Writing 52692 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0051 starting from device address 0x0000 ...

    Reading 52692 bytes from EEPROM bus address 0x0051 to DSP memory address 0x0c010000 starting from device address 0x0000 ...

    Verifying data read ...

    EEPROM programming completed successfully.

    3) Use NAND writer to write an ELF into NAND. If you want to demo UART is working, you can use the C:\ti\mcsdk_2_01_02_06\tools\post\evmc6678l\bin\post_evm6678l.out. First load this via CCS and run to make sure you can see output at UART.

    To write this to NAND, simply rename it to app.bin and load into address 0x80000000. Make sure you have gel file to init DDR3.

    [C66xx_0] NAND Writer Utility Version 01.00.00.00

    Flashing block 1 (0 bytes of 518706)

    Flashing block 2 (16384 bytes of 518706)

    Flashing block 3 (32768 bytes of 518706)

    Flashing block 4 (49152 bytes of 518706)

    Flashing block 5 (65536 bytes of 518706)

    Flashing block 6 (81920 bytes of 518706)

    Flashing block 7 (98304 bytes of 518706)

    Flashing block 8 (114688 bytes of 518706)

    Flashing block 9 (131072 bytes of 518706)

    Flashing block 10 (147456 bytes of 518706)

    Flashing block 11 (163840 bytes of 518706)

    Flashing block 12 (180224 bytes of 518706)

    Flashing block 13 (196608 bytes of 518706)

    Flashing block 14 (212992 bytes of 518706)

    Flashing block 15 (229376 bytes of 518706)

    Flashing block 16 (245760 bytes of 518706)

    Flashing block 17 (262144 bytes of 518706)

    Flashing block 18 (278528 bytes of 518706)

    Flashing block 19 (294912 bytes of 518706)

    Flashing block 20 (311296 bytes of 518706)

    Flashing block 21 (327680 bytes of 518706)

    Flashing block 22 (344064 bytes of 518706)

    Flashing block 23 (360448 bytes of 518706)

    Flashing block 24 (376832 bytes of 518706)

    Flashing block 25 (393216 bytes of 518706)

    Flashing block 26 (409600 bytes of 518706)

    Flashing block 27 (425984 bytes of 518706)

    Flashing block 28 (442368 bytes of 518706)

    Flashing block 29 (458752 bytes of 518706)

    Flashing block 30 (475136 bytes of 518706)

    Flashing block 31 (491520 bytes of 518706)

    Flashing block 32 (507904 bytes of 518706)

    Reading and verifying block 1 (0 bytes of 518706)

    Reading and verifying block 2 (16384 bytes of 518706)

    Reading and verifying block 3 (32768 bytes of 518706)

    Reading and verifying block 4 (49152 bytes of 518706)

    Reading and verifying block 5 (65536 bytes of 518706)

    Reading and verifying block 6 (81920 bytes of 518706)

    Reading and verifying block 7 (98304 bytes of 518706)

    Reading and verifying block 8 (114688 bytes of 518706)

    Reading and verifying block 9 (131072 bytes of 518706)

    Reading and verifying block 10 (147456 bytes of 518706)

    Reading and verifying block 11 (163840 bytes of 518706)

    Reading and verifying block 12 (180224 bytes of 518706)

    Reading and verifying block 13 (196608 bytes of 518706)

    Reading and verifying block 14 (212992 bytes of 518706)

    Reading and verifying block 15 (229376 bytes of 518706)

    Reading and verifying block 16 (245760 bytes of 518706)

    Reading and verifying block 17 (262144 bytes of 518706)

    Reading and verifying block 18 (278528 bytes of 518706)

    Reading and verifying block 19 (294912 bytes of 518706)

    Reading and verifying block 20 (311296 bytes of 518706)

    Reading and verifying block 21 (327680 bytes of 518706)

    Reading and verifying block 22 (344064 bytes of 518706)

    Reading and verifying block 23 (360448 bytes of 518706)

    Reading and verifying block 24 (376832 bytes of 518706)

    Reading and verifying block 25 (393216 bytes of 518706)

    Reading and verifying block 26 (409600 bytes of 518706)

    Reading and verifying block 27 (425984 bytes of 518706)

    Reading and verifying block 28 (442368 bytes of 518706)

    Reading and verifying block 29 (458752 bytes of 518706)

    Reading and verifying block 30 (475136 bytes of 518706)

    Reading and verifying block 31 (491520 bytes of 518706)

    Reading and verifying block 32 (507904 bytes of 518706)

    NAND programming completed successfully

    4) Set card in NAND boot mode, you should see similar UART output ....

    IBL version: 1.0.0.15                                                     
    IBL: PLL and DDR Initialization Complete                                       
    IBL Result code 00                                                             
    IBL: Booting from NAND                                               
                                                                                    
                                                                                   
    TMDXEVM6678L POST Version 01.00.00.04                                          
    ------------------------------------------                                     
    SOC Information                                                                
                                                                                   
    FPGA Version: 000D                                                             
    Board Serial Number: EPD0065321                                                
    EFUSE MAC ID is: 40 5F C2 B9 48 A1                                             
    SA is enabled on this board.                                                   
    PLL Reset Type Status Register: 0x00000001                                     
    Platform init return code: 0x00000000                                          
    Additional Information:                                                        
       (0x02350014) :00000000                                                      
       (0x02350624) :000211F

    Regards, Eric

     

  • 0 in reply to lding
    Prodigy 70 points

    Hi Eric,

    I have problem with point one with re-build IBL. I have changed src file device.c as you wrote, but i can´t re-build it and get file iblConfig.out. I start command line and get to path mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util\iblConfig\build and wrote

    make EVM=c6678l I2C_MAP_ADDR=0x500 and i got

    gcc -c -O2 -DEVM=c6678l -DI2C_MAP_ADDR=0x500 -I../src ../src/device.c -o obj/device.obj

    process_begin: CreateProcess(NULL, gcc -c -O2 -DEVM=c6678l -DI2C_MAP_ADDR=0x500 -I../src ../src/device.c -o obj/device.obj, ...) failed.

    make (e=2): System can not find reffered file.

    make: *** [obj/device.obj] Error 2

    Point 3)

    Make sure you have gel file to init DDR3.

    First i load program nandwriter_evm6678l.out to core 0, then i load GEL Files evmc6678l.gel, console show me C66xx_0: GEL Output: Setup_Memory_Map...
    C66xx_0: GEL Output: Setup_Memory_Map... Done and then i load my own program on address 0x80000000.

    Is this correct?

    Thank you.

    Sincerely,

    Petr Kriz

  • 0 in reply to sulvan
    TI__Guru* 95265 points

    Petr,

    The steps to re-build IBL is documentated in \tools\boot_loader\ibl\doc\build_instructions.txt.

     make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51.

    The output .bin (around 52KB in size) is the one you need to write to EEPROM 0x51. 

    Regards, Eric

     

  • 0 in reply to lding
    Prodigy 70 points

    Ok,

    I will try it.

    I would like ask you on start address and brunch address for my mcsdk for gel file? Thank you.

    Sincerely,

    Petr Kriz

  • 0 in reply to sulvan
    TI__Guru* 95265 points

    Petr,

    You need to run Global_Default_Setup in GEL before using DDR.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 70 points

    Hi Eric,

    I am not able build ibl. I went throw manual in \tools\boot_loader\ibl\doc\build_instructions.txt. I have installed mingw32, modified setupenvMsys.sh, start MinGw Shell, set path to ibl\src\make and wrote make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51. After that many mistakes appears.

    As you wrote:

    1) mcsdk_2_01_02_06\tools\boot_loader\ibl\src\util\iblConfig\src\device.c, edit this file by changing ibl_t c6678_ibl_config(void) ====> if you are using 6678.   
      ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_ELF;

    Re-build IBL.

    in official manual is only modifying i2cConfig.gel and uploading it throw i2cparam_0x51_c6678_le_0x500.out program.

    Please, could you write me again detailed instructions? I think, as i wrote first, my boot loader work correct, but i have problem write my program correctly into the nand memory. Maybe there is problem with addresses. I would like to know start address and brunch address for my mcsdk for gel file?

    Thank you.

    Sincerely,

    Petr Kriz

  • 0 in reply to sulvan
    Intellectual 375 points

    As for start address and branch address in i2cConfig.gel, I found that they are 0x9E000000 and 0x9E001040 for MCSDK_02_00_05_17:

    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x9E000000; 

    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x9E001040;

    But I have no idea about these addresses for your MCSDK 02_01_02_06. Maybe anybody from TI can help us ?

  • 0 in reply to sulvan
    TI__Guru* 95265 points

    Petr,

    There is no difference in the NAND start address and brunch between the i2cConfig.gel and device.c file for 6678.

        ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Image 0 load start address in LE mode */
        ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xFFC000;         /* Image 0 size in LE mode */
        ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in LE mode */

    If you have trouble to build IBL and want to use the steps from official manual. And you think the you have issue to write your program into NAND.

    Then, steps:

    1) Put you EVM in no boot mode

    2) In target configuration file for your 6678 emulator, add the gel file to core 0.

    3) connect core 0, the following shall be seen:

    Connecting Target...

    C66xx_0: GEL Output: DSP core #0

    C66xx_0: GEL Output: C6678L GEL file Ver is 2.0

    C66xx_0: GEL Output: Global Default Setup...

    C66xx_0: GEL Output: Setup Cache...

    C66xx_0: GEL Output: L1P = 32K

    C66xx_0: GEL Output: L1D = 32K

    C66xx_0: GEL Output: L2 = ALL SRAM

    C66xx_0: GEL Output: Setup Cache... Done.

    C66xx_0: GEL Output: Main PLL (PLL1) Setup ...

    C66xx_0: GEL Output: PLL in Bypass ...

    C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.

    C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.

    C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.

    C66xx_0: GEL Output: PLL1 Setup... Done.

    C66xx_0: GEL Output: Power on all PSC modules and DSP domains...

    C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.

    C66xx_0: GEL Output: PA PLL (PLL3) Setup ...

    C66xx_0: GEL Output: PA PLL Setup... Done.

    C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...

    C66xx_0: GEL Output: DDR3 PLL Setup... Done.

    C66xx_0: GEL Output: DDR begin (1333 auto)

    C66xx_0: GEL Output: XMC Setup ... Done

    C66xx_0: GEL Output:

    DDR3 initialization is complete.

    C66xx_0: GEL Output: DDR done

    C66xx_0: GEL Output: DDR3 memory test... Started

    C66xx_0: GEL Output: DDR3 memory test... Passed

    C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...

    C66xx_0: GEL Output: configSGMIISerdes Setup... Begin

    C66xx_0: GEL Output:

    SGMII SERDES has been configured.

    C66xx_0: GEL Output: Enabling EDC ...

    C66xx_0: GEL Output: L1P error detection logic is enabled.

    C66xx_0: GEL Output: L2 error detection/correction logic is enabled.

    C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.

    C66xx_0: GEL Output: Enabling EDC ...Done

    C66xx_0: GEL Output: Configuring CPSW ...

    C66xx_0: GEL Output: Configuring CPSW ...Done

    C66xx_0: GEL Output: Global Default Setup... Done.

    4) Use CCS memory window to address 0x8000_0000 to make sure you can poke this address.

    5) Load the nandwriter

    6) rename your .out file to .bin file

    7) load .bin file to address starting with 0x8000_0000, you should see 0x8000_0000 and following address contents changed in memory window

    8) run your nandwriter to finish

    9) Power on the EVM

    10) change to NAND boot mode and power ON

    Regards, Eric

  • 0 in reply to lding
    Prodigy 70 points

    Hi Eric,

    thank you for your help. It finally starts work. My problem was in no initialized DDR memory. I forgot include evmc6678l.gel file to the target configuration file so i couldn´t see GEL procedure as you wrote.