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How to judge whether the DMA controller is in use or not of AM335x?

I want to let the AM335x enter more low power consumption when it is in idle mode as following method:

1. In Linux, OS schedule a idle task to let CPU enter WFI mode.

2. I've modified the code of the idle task, before CPU enter WFI mode, I'll put the PLLs of Core and MPU enter bypass mode.

kernel code:

local_irq_disable();
do_gettimeofday(&before);
cpu_do_idle();
do_gettimeofday(&after);
local_irq_enable();

The function "cpu_do_idle" shall let CPU enter "WFI" mode.

modified kernel code:

local_irq_disable();
do_gettimeofday(&before);

core_mpu_pll_bypass();
cpu_do_idle();

core_mpu_pll_restore();
do_gettimeofday(&after);
local_irq_enable();

The function "core_mpu_pll_bypass" shall let the PLLs of core and MPU enter bypass mode, the function "core_mpu_pll_restore" shall let the PLLs of core and MPU resume.

3. Added the PLLs of Core and MPU enter bypass mode, the power consumption of idle state is less than WFI only mode.

4. In my opinion, idle task is only handle the CPU idle. When CPU idle, DMA maybe works. If I put the PLL of core to bypass mode when cpu idle, it could reduce the DMA speed if there is a DMA transfer but cpu is idle. So I need to figure out the DMA status(it works or not) to bypass the PLL of core or not. If DMA works, the idle task shall not bypass the PLL of core.

Does anyone know how to judge whether the DMA controller is in use(DMA works or not)? It seems that there is no register related.

  • You may be able to use the CCSTAT register to determine when the Channel Controller is active.  However, i would caution trying to have software to react to reading this status.  The latency of software running on the ARM may be too much to really synchronize any meaningful operation you may want to do. 

    I would try to conform to using the low power modes supported by our SDK (Standby and/or DeepSleep0).  One of these should be able to meet your power consumption needs.

    regards,

    James