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mcsdk video sv04 demo

Tushar Paithankar
Intellectual 520 points


Hi,

1. How the master core communicate with other cores in MSCDK video sv04 demo (Through PCIe)....?

2. And how the job is divided in same case between the cores....?

Regards

Tushar

  • 0
    TI__Mastermind 40110 points

    Hi Tushar

    1) Multicore codecs use Multicore Video Interface APIs (ividMC). This APIs define barriers, share memory allocation, locks etc.

    2) Task division depends on the codec.

    - A symmetric Task division: For example H.264 encoder. Here each core encode an slice of the frame (data partition). Master core has some extra additional light tasks in order to stick together slaves' outputs and add some headers.

    - An asymmitric task division: For example h.264 decoder. Here some functions are implemented on the master and others in the slave. Both cores work in pipeline with sync points.

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 40110 points

    Hi Tushar please let us know if you have further questions or if we can close this thread. Thanks

    Paula

  • 0 in reply to Paula Carrillo
    Intellectual 520 points

    Hi Paula,

    Sorry for late replay,  Can u tell me is it possible to run encoder on different core and decoder on different core of same DSP.

    If yes how, means what changes we have to do for that.

    Thanks

    Tushar

  • 0 in reply to Tushar Paithankar
    TI__Expert 4335 points

    Hi Tushar,

    Yes, it is possible to run multi-core decoder and multi-core encoder on a single C6678 DSP. As in the demo overview of MCSDK Video 2.1 (http://processors.wiki.ti.com/index.php/MCSDK_VIDEO_2.1_Demo_Guide#Ethernet_Based_Demos), "Multi-core 1080p Transcoding Demo" uses core 6 and core 7 to decode 1080p30 H264BP stream. Then, the decoded YUV frame is encoded by core 0,1,2,3 as 1080p30 H264BP stream. In this demo, the decoding is through H264HP decoder, and the encoding is done with H264BP encoder.

    The above transcoding is implemented in MCSDK Video 2.1.0.8 under dsp/siu/video folder. Multi-core decoding starts from siuVigdkRxVideoDecoderProcess(). In siuRxVideoMasterDecode, the master core sends the necessary information to the slave core via IPC-MessageQ, and then triggers decoder process call. Slave core receives the message from the master core, and then enters siuRxVideoSlaveDecode()  to trigger the decoder process call. After the decoding is completed, master core calls siuVigdkShipoutYUV() to communicate the decoded YUV to master encoding core. The communication here is again through IPC_MessageQ. 

    When master encoding core receives the core2core message, it enters siuTxVideoEncoderProcess() and calls siuTxVideoMasterEncode(). Similar to the decoding, the master core  sends the necessary information to the slave core(s) via IPC-MessageQ, and then triggers encoder process call. Slave core(s) receive the message from the master core, and then enter siuTxVideoSlaveEncode()  to trigger the encoder process call. After the encoding is completed, master core sends the encoded stream to network.

    Top-level functions for the above call flow can be found from siuVigdkRxVideo.c, siuVigdkTxRx.c, and siuVigdkTxVideo.c.

    If you would like to step into the code, you can comment out the optimization flags in dsp/mkrel/c64x/makedefs.mk: #C_OPT_FLAGS  = -mt -mw -os -o3 --optimize_with_debug, and then rebuild sv01.out to run the "Multi-core 1080p Transcoding Demo". Note that this demo is verified on standalone EVM TMDXEVM6678LXE with Windows PC.

    Thanks,

    Hongmei