DSK C6713 External interrupt polarity

Hi Arjay,

Thanks for your post.

Please refer the below link for "TMS320C6000 Chip Support Library API Reference Guide" - Chapter 14 covers the IRQ Module which, if you are not using DSP/BIOS, can be used to configure and handle interrupts and Kindly check for Section B.10.3 External Interrupt Polarity Register (EXTPOL) to configure the same.

http://www.ti.com/lit/ug/spru401j/spru401j.pdf

Thanks & regards,

Sivaraj K

Perhaps the following excerpt from my own vector.asm will help:

 

 

; C6713 maskable interrupt (# 4..15) operation:

; The C6713 by default expects any external interrupt (4..7) source to

; issue a low-to-high transition to request an interrupt (to set the

; corresponding IFR bit).  However, the DSK board and its peripheral

; evaluation modules maintain the external interrupt lines at HIGH logic

; level, and assert an interrupt request by pulling the line LOW (a high-

; to-low transition).  Fortunately, there are ways of reversing the

; effective signal polarity.

;

; The C6713 has MUXL/MUXH registers to map interrupt sources to interrupt

; "levels" (priority numbers), and an EXTPOL register for programming

; external interrupt trigger polarity.  We plan to use just the default

; source configuration, and to set the EXTPOL bits for high-to-low

; triggering.

; An interrupt source sets a bit in the IFR to request an interrupt.  In

; the case of interrupts that share pins with the GPIO subsystem, the

; corresponding bit in GPEN must be set, and the same bit in GPDIR must

; be 0 (input mode).

; An interrupt is triggered when all of the following are true:

; (1)  The corresponding bit is set in IFR (reflects source request).

; (2)  The corresponding bit is set in IER (maintains program control).

; (3) The NMIE bit is set in IER; once set it cannot be cleared except by

;      RESET, or during execution of a handler triggered by NMI.

; (4)  The GIE bit is set in CSR.

; The ISTP register must be pre-set to point to the base of an Interrupt

; Service Table, which is an array of 16 interrupt vectors; each vector is

; an 8 instruction-word long "fetch packet".  To process any interrupt

; other than RESET, the state of the GIE bit is copied into the PGIE bit

; and then cleared, thereby inhibiting further interrupts (except for NMI,

; which we don't use, and RESET).  The program counter is saved in the IRP

; register, and processor execution is redirected to the start of the

; vector corresponding to the highest-priority (lowest-numbered) interrupt

; source (see list at end of this file) for which the corresponding bit in

; IFR & IER is set, after clearing that bit of IFR.  The vector is located

; at (ISTP & ~0x3FF) + (32 * interrupt_number), which is actually stored

; in ISTP up to the point that the IFR bit is cleared.  Note that no

; registers have yet been saved, and no stack has yet been used.

; The C compiler generates appropriate register save/restore linkage when

; a handler function (aka "interrupt service routine", or ISR) is defined

; with the "interrupt" qualifier: "interrupt void handler(void) { ... }".

; An ISR has no arguments and returns no value.  Upon return, it restores

; whatever registers it used and branches to the location in IRP, which

; restores the original GIE bit and resumes the interrupted computation.

; Non-maskable interrupt (NMI) uses vector # 1, and differs from normal

; interrupts in that the return PC is saved in NRP instead of IRP, PGIE

; and GIE are unaffected, and the NMIE buy in IER is cleared, which blocks

; all other non-RESET interrupts.  The NMI interrupt handler must return

; by branching to the location in NRP.

; It is assumed that the run-time stack (pointed to by B15) has room for

; whatever local variables are used by the handler.  If the stack is

; overrun, the result will most likely be catastrophic.  You can fill the

; stack with a pattern such as 0x5A5A5A5A and, after program execution,

; examine the lowest stack contents with a debugger to verify that the

; stack limit was never reached (pattern still intact).

; Care must be taken to avoid spurious interrupt transitions when enabling

; the GPIO subsystem, when clearing or setting GPIO registers, and when

; toggling the polarity registers.  (An IFR bit will be set if the

; appropriate transition is seen; once set, the IFR bit remains set until

; either it is cleared by writing to the ICR or the interrupt is

; triggered.)  A suitable policy is to change the registers while

; interrupts are disabled, then clear any potentially affected bits in IFR

; before re-enabling interrupts.

; A typical active interrupt vector looks like this:

vector

.macro addr ; (this macro is not actually used in this file)

.ref addr

; C interrupt handler function (ISR)

; (declare with "interrupt" linkage)

; .align 32 ; should already be satisfied

STW .D2 B0,*B15--[2]

; save B0 temporarily on the stack

; (SP must always be 8-byte aligned)

|| MVKL .S2 addr,B0 ; load ISR address

MVKH .S2 addr,B0

B .S2 B0 ; start ISR execution

LDW .D2 *++B15[2],B0

; restore B0 and stack pointer B15

; (original B0 reaches RAM here)

NOP 4 ; fill branch's and load's delay slots

* ; (branch occurs here)

* ; ISR returns from intr via "B IRP"

NOP ; (not executed)

NOP ; (not executed)

.endm ;vector