dMAX register access during transfer in progress

Hi,

Refer the TMS320C672x DSP Dual Data Movement Accelerator (dMAX) Reference Guide
http://www.ti.com/lit/spru795

Here RLOAD bits defines for FIFO read and write sequence in Event Entry for FIFO Transfer Register.

Hi Pubesh,

I have read the guide you pointed to many times.  In my original post I am quoting text from that guide.  I am not using FIFO transfers, I am using General Purpose transfers.  I really want more information on this text:

"It is not recommended to access the active register set, indexes, reference counter (within the transfer entry), or event entry of a transfer in progress."

What does "not recommended" mean?  Does this mean there are conditions under which we can access these registers during a transfer in progress?  Can we read these registers, but not write these registers?  What are the consequences of accessing these registers during a transfer in progress?

Thanks.

Hi,

I understood from your reply, You are working for general purpose transfers.
From the spru795, you can get the sequences and transfer examples.
General purpose transfer have 1D, 2D and 3D transfers with examples under the section "3.2.1 Steps Required to Set Up a General Purpose Transfer"
I think, it will give the details for your query.

I have no trouble configuring the dMAX.  In my software I have many transfers taking place successfully.  Both memory to memory and memory to McASP port transfers.  I do not need any help with configuring a dMAX transfer.  I am looking for very specific information about this note in the TI guide:

"It is not recommended to access the active register set, indexes, reference counter (within the transfer entry), or event entry of a transfer in progress."

Please see my specific questions in the last post.  Can you, or someone else at TI, answer these?

Thanks.

Hi,

During a transfer, dMAX uses the active register set and the reference counter.
If reload is enabled at the end of the transfer, active address registers are loaded from one of two sets of reference address registers.
The address reference register set used during reload is specified by the PP bit within the transfer entry.

The event must be enabled by setting a corresponding bit in the DEER.
Once an event is enabled, dMAX will perform a data transfer after an appropriate transition is detected on the event signal.

After enabling the event, it is not recommended to access the event entry, active register set, indexes, and the reference counter bit fields within the transfer entry.

CT,

CT45036 said:

What does "not recommended" mean?  Does this mean there are conditions under which we can access these registers during a transfer in progress?  Can we read these registers, but not write these registers?  What are the consequences of accessing these registers during a transfer in progress?

"not recommended" is not the same as "must not" or "shall not" or "it is okay" or "it does not matter". "not recommended" means exactly what you already understand it to mean: TI's advice is to not do these things; you can do these things and it might work but it might fail. We choose our wording carefully, for example saying not to "access" these areas instead of saying not to "write" these areas.

TI takes care to document how to do things correctly, in ways that we have tested, so that you can have quick success in your program. If you want to use the examples and recommendations from TI, then we can stand behind your success and your success will come quickly.

If you want to deviate from our recommendations, you are obviously within your rights as a programmer. We have not necessarily tested things outside of our recommendations and examples, but there are an endless number of ways that this powerful dMax module can be used.

TI does not always document or test every other way that the device could be used. In our testing and experience, it is common to run into trouble doing a certain test. We make changes that eliminate the problems and offer the final working examples and practical recommendations that we have learned and developed.

Pubesh has explained more details about how the dMax works. You can draw some inferences from those, but we cannot make any direct claims to address your questions that are outside of what we have documented and recommended for you.

It seems clear that there could be cases where writing to these registers at teh wrong time could cause a failure if that register is also being written or read by the dMax during execution. It is less clear why a read would cause a failure, but I can certainly testify that over the years I have seen cases where any access at a particular clock cycle could cause something to shift by one clock cycle and throw off another operation. I have no reason to speculate this on the dMax based on fact, but I am just saying that some strange things are possible.

If you choose to deviate from this recommendation, be sure to do a lot of testing on the code. Develop tests that vary the time or phase delay from the start or end of the transfer to these accesses that you want to do. Your thorough testing is what will assure your program will work, since TI has not tested it that way.

We are not saying it will not work, but we are saying that our recommended method will work. And we are sorry that we cannot document for you what will fail when you do things counter to our recommendations. If someone else has experience using the dMax as you are looking to do, maybe they will jump into this discussion to give you their advice.

Regards,
RandyP