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Data movement from DSP to ARM using EDMA

cassiewang
Prodigy 50 points

Hi, 

I would like to send data from DSP to ARM (TI814x) in a shared memory using EDMA (for some reason, we cannot use IPC). I searched this topic in the forum and found in this post http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/48908/216386.aspx a similar problem was already discussed. But I still did not fully understand. Hope that I can get some help here.

My questions are as follows:

1)      DSP sets up an EDMA operation. When the operation is done, will EDMA trigger an interrupt on DSP or on ARM or on both side?

2)      Both DSP and EDMA have the interrupt service routine corresponding to the transfer completion. But if ARM-service routine takes longer time or reacts too late, how to synchronize the data transfer?

3)      In the linked post it was answered “This can be done. The EDMA controller has 2 completion interrupt, one mapped to ARM and one mapped to DSP (Recommend looking at Section 2.9.1.1 in the EDMA user guide). Region 0 interrupt goes to ARM and Region 1 interrupt goes to DSP. So you could setup your TCC values (completion code) and DRAE registers such that on completion of the ARM based EDMA transfer, the EDMA3 interrupt triggered is Region 1 interrupt going to DSP.”  I didn’t understand it. Does that mean for the data transfer between two cores EDMA controller will generate 2 completion interrupts (one for ARM and one for DSP)? But as far as I understood for the shadow region, each EDMA channel can be mapped only to one region. So, how can I realize this?

 Thanks, 

Cassie

  • 0
    Expert 1550 points

    Hi Cassie,

    Not clearly understood ur scenario , but what i understood is u r configuring EDMA from DSP and want this data to be made available to ARM. 

    Not exactly similar but closely related scenario we had , so :-

    1)  The EDMA controller transfers the data and interrupts to DSP...so the DSP can handle the data after transfer is completed. 

          So for u ..u can have the EDMA interrupt ARM .

          In Arm u can have an ISR being registered to handle the interrupt and get the data transferred which was dumped by EDMA. 

    2) Also u can have an mutually accepted DDR section where , the EDMA [from DSP]  will dump the data. 

        An data from same memory can be fetched from ARM ..

    This i am not sure will be helpful as there will be need to have some mechanism between ARM completing the data

    read in response to interrupt and DSP starting the EDMA again...

    3) For synchronization u may use FLAGGING mechanism between DSP and ARM ...

    So even though these will simplify the development and analysis , the THROUGHPUT will suffer.

    So it will be an call between simplicity and THROUGHPUT expected.

    Ashish Mishra 

    [Banglore /INDIA ]

     

  • 0 in reply to Ashish Kumar Mishra
    Prodigy 50 points

    Hi Ashish, 

    thank you for your quick response.

    Ashish Mishra1 said:

    1)  The EDMA controller transfers the data and interrupts to DSP...so the DSP can handle the data after transfer is completed. 

          So for u ..u can have the EDMA interrupt ARM .

          In Arm u can have an ISR being registered to handle the interrupt and get the data transferred which was dumped by EDMA. 

    May I ask, the EDMA interrupt ARM and DSP both? or only ARM? any configuration should I do for interrupting both side? Do we need to set any shadow region?

    Ashish Mishra1 said:

    3) For synchronization u may use FLAGGING mechanism between DSP and ARM ...

    So even though these will simplify the development and analysis , the THROUGHPUT will suffer.

     

    Why the THROUGHPUT will suffer? 

    thanks again, 

    Cassie

  • 0 in reply to cassiewang
    Expert 1550 points

    Hi Cassie , 

    1.  i have not used ARM interrupt from DSP side , but going through some queries on forum

          they say that it can be done . 

         U can focus on shadow region as to how to use it .... i am not well versed for that part. ...

         

    2. The reason i said THROUGHPUT will suffer is because :- 

        a) The EDMA transfer is completed on DSP and Interrupt is generated to ARM. 

        b) In response to EDMA the ARM will start reading the stored data from pre-defined section

             of memory [where EDMA has dumped data ]

        Now in this model of behavior , you can't start EDMA from DSP  in time interval

         "After step A ...till step B is completed "...


        Because after step "a" ....DSP will raise the flag which needs to be detected by ARM  , then

        ARM will read the data , then ARM will again inform 

        DSP that it had read the data ....... 

    So only after this chain is completed , you can start EDMA again .....now as you see the engine

    will be like OP1---OFF---OP2---OFF---OP3---OFF 

    So the Off period will cause the decrease in throughput ....ideally it should be OP1---OP2---OP3

    Ashish Mishra 

    [Banglore /India]

  • 0 in reply to Ashish Kumar Mishra
    Prodigy 50 points

    Thank you very much Ashish, 

    now I understand why the THROUGHPUT suffers. 

    Regards,

    Cassie




  • 0 in reply to cassiewang
    Expert 1550 points

    Hi Cassie , 

    An request to u is to let us know steps to configure EDMA interrupt to ARM  ... once you have verified the steps.


    Thanks 

    Ashish Mishra 

  • 0 in reply to Ashish Kumar Mishra
    TI__Mastermind 20790 points

    Cassie and Ashish,

    Refer the section 8.4.9 EDMA3 Interrupts in TRM as mentioned below link,
    http://www.ti.com/lit/sprugz8

    1. Transfer completion Interrupt
    2. Error Interrupt

    The transfer completion interrupts and the error interrupts are all routed to the DSP and ARM interrupt controllers.
    The EDMA3CC is responsible for generating transfer completion interrupts to the CPU (EDMA3 masters).
    TCC value is directly mapped to the bits of the interrupt pending register(IPR/IPRH).

    For the ARM and the DSP, you can also use the shared ram or the external memory,
    http://software-dl.ti.com/dsps/dsps_public_sw/sdo_tii/psp/edma3_lld/index.html

  • 0 in reply to Pubesh
    Prodigy 50 points

    Hi Pubesh, 

    Thank you for your response.

    Pubesh said:
    The transfer completion interrupts and the error interrupts are all routed to the DSP and ARM interrupt controllers.

    The EDMA3CC is responsible for generating transfer completion interrupts to the CPU (EDMA3 masters).
    TCC value is directly mapped to the bits of the interrupt pending register(IPR/IPRH).

    May I ask in this case which side is EMDA3 master? ARM or both ARM and DSP are masters?

    Do I need to configure something in shadow region for setting one core as the master? 

    thanks, 

    Cassie

  • 0 in reply to cassiewang
    TI__Mastermind 20790 points

    Cassiewang,

    The EDMA controller has two completion interrupt.

    Oone mapped to ARM(Region 0 interrupt ) and one mapped to DSP( Region 1 interrupt).

    You can setup TCC values and DRAE registers( ARM based EDMA tranfer). However EDMA3 interrupt triggered is Region 1 interrupt going to DSP.

    I do not see configure as the master through shadow region.

  • 0 in reply to Pubesh
    Prodigy 50 points

    Hi Pubesh, 

    I understand, thank you very much.  

    Regards,

    Cassie