DM8148 BT.601

When you say "cannot work well" what exactly happens?

The only real difference between the 2 standards is that 601 uses discrete syncs but 656 uses embedded syncs.

I think it should be possible to enable discrete syncs with 8 bit single channel output. Check the HDVPSS documentation included in the RDK for more information.

I am not a software person so can't help much more on the configuration side, but I do think this should be doable.

Dear Sir:

  I say "can not work well" mean the color is incorrect. We use the color bar to verify it. And I also know the difference between 601/656 is the sync, the 601 is based on external sync, 656 is based on the embed-sync within the data pin. The color output we see is something like the post "http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/211072.aspx"

In 8148 datasheet, sprs647d.pdf, section 3.2.23 Video Output (Digital), the description of VOUT[0]_G_Y_YC[2-9], VOUT[0]_B_CB_C[2-9], and VOUT[0]_R_CR[2-9] shows what I thought. In spruhi7.pdf, HD_VENC_D_cfg0 Register Field Descriptions DVO_FMT also describes the 1CH/2CH/3CH type, but no 1CH discrete-sync.

Because I don't see any other detail descriptions in the datasheet for DVO so I am not sure what I thought is correct or not.

However in the spruhi7.pdf, 1.2.7.5.1 Output Formats of DVO, based on the table 1-46.

The DVO_D0/DVO_D1/DVO_D2 I thought should represent VOUT[0]_G_Y_YC[2-9], VOUT[0]_B_CB_C[2-9], and VOUT[0]_R_CR[2-9] then the table explains when on DVO_D0 is desired to output YCbCr only BT656 mode is supported.

  Finally, before I post the question,  I did read the code through the RDK, however they did not support the 480I output from DVO2.

  If my concept for the DM81xx is incorrect, please correct me.

Regards,

It might be necessary to modify the driver to support 601. If you configure for 1 channel x 8 bit (i.e. 656) what result do you get?

It may be possible to enable the discrete syncs through pin mux configuration independently of the driver.

I am not a software person so can't comment more unfortunately.

BR,

Steve

Dear Steve:

  Thanks for the reply, I did configure the pinmux to allow the CPU output clk/hsync/vsync/actvid ... etc., however, when we need to use a 8 bit output, and configure it to BT656 mode, then one kind of the sync(I forgot it;s vsync or hsync) disappear. And due to the panel only support the BT601, then it only output the color bar in wrong color like the thread in others post. Due to I did not see any datasheet/register manual that can set the BT601 in 8 bit mode, only 16bit or 24 bit mode in the manual so I post the question here.

  One more question I would like to know is that we connect the panel LSB D0 to D7 to CPU VOUT0_B_CB_C[2] to VOUT0_B_CB_C[9], is this correct? I just want to make sure the LSB output from CPU is identical as in the panel.

Regards,

I am surprised that you get anything at all displayed if you do not send syncs to the LCD.

I have asked the software team to help with the pin mux configuration, but you need to make sure that the pin mux is configured after setting 656 mode since I suspect that the driver will set all the pin mux as per 656 when it is called.

Regarding the color bits, yes you should take the MSB of the output channel.

BR,

Steve

Dear Steve:

  Thanks for the reply, however, the PINMUX is okay because before we tried the 1CH BT656, we use the 2CH/3CH Discrete-sync, and it show the VSYNC/HSYNC/PCLK are all okay. And the driver did not set the pinmux after the initial. The RDK only setup it once, and we also set it up before by following the datasheet. we used.

Regards,

/ckhsu

Hi CK,

Pinmux is already set in the driver, so there is no need to set it. If the colors are not correct, it could be some configuration issue. Could you share dump of memory from 0x4810A000 (25 words)?

Regards,

Brijesh Jadav

I am a little confused?

In order to effectively configure for ITU601 you need to configure for ITU656 then manually enable the H, V & F outputs after setting 656 mode. Is this what you did?

I am very surprised you get any display at all if you do not configure the H, F & V.

The output pins used will change whenever you call the sysfs entry to change the format, for example 2ch or 3ch since they need different number of pins.

I am not sure what you mean by "PINMUX is okay because before we tried the 1CH BT656, we use the 2CH/3CH Discrete-sync, and it show the VSYNC/HSYNC/PCLK are all okay" ? Then you used 1ch 656 mode the H, F & V will not be active. When you use sch or 3ch then it will not be single channel 8bit output. These are mutually exclusive.

BR,

Steve

Hi Brijesh:

  Thank you for the reply, the below are our setting for DVO2 HDVENC. Due to the panel can only support the BT601 8 bit mode, but DM81xx only support BT656 in 8 bit mode not the BT601, so we can only  set it in 1CH BT656. However when set in BT656 mode with STEST bit, we can see the color bar with incorrect color on the BT.601 LCD, so maybe there are still chances can make the LCD display correct.

CFG0 = 0x4400B058
CFG1 = 0x003f0275
CFG2 = 0x1ea500bb
CFG3 = 0x1f9901c2
CFG4 = 0x1fd71e67
CFG5 = 0x304001c2
CFG6 = 0xff200200
CFG7 = 0x1b6c0b35
CFG8 = 0x1c0c0c30
CFG9 = 0x1c0c0c30

CFG10 = 0x8420d6b4
CFG11 = 0x7c11c015
CFG12 = 0x7c5a80eb
CFG13 = 0x00000105
CFG14 = 0x00038338
CFG15 = 0x7c5a0114
CFG16 = 0x00016000
CFG17 = 0x000f011c
CFG18 = 0x030040f0
CFG19 = 0x0300110d
CFG20 = 0x0010e10a
CFG21 = 0x7c5a010c
CFG22 = 0x00016001
CFG23 = 0x000f011c
CFG24 = 0x030010f0
CFG25 = 0x030040fa

Hi Steve:

  Since the datasheet did not say the 8 bit mode support the BT601 but only 16/24 bit mode, so we can only configure it in BT656 mode.

And we first configure DVO2 in 16bit BT601 to make the Panel receive the PCLK/HSYNC/VSYNC, then we configure the DVO2 to be BT656. We configure the register directly in the module and wait there to see the result rather than through the sysfs.

Regards,

/ckhsu

Hi,

As such, register configuration looks correct. i have not checked the CSC settings, but output format is YUV and CSC is enabled. If you are using sysfs entries for configuring this VENC, then CSC settings will also be correct. one more check, could you check what is the input format supported by your LCD? is it YUYV, YVYU. UYVY or VYUY?

Regards,

Brijesh

Hi Brijesh:

  Thanks for the reply.

  The panel YUV sequence is default in CbYCrY, and it can be set through SPI. By using the SPI.1, we set the possible 4 outputs CbYCrY/YcrYCb/CrYCbY/YcbYCr, and none of the sequence output the correct color bar, in fact they output 2 different color bar.

  And we also tried to bypass the color space in CFG0, however, the result is still incorrect.

Regards,

/ckhsu

If you are configuring for 16 bit, then trying to change back to embedded sync then my guess is that you are not changing all the required clocks etc...

My recommendations is as I mentioned previously, to set 656 mode initially then enable the syncs manually after setting 656 mode through sysfs entries. This ensures all internal clocks and processing paths are set as close as possible to ITU601.

Once you have done this check the H, F & V with an oscilloscope to make sure they are wiggling.

BR,

Steve

Hi Brijesh:

  Sorry to reply late because we are looking for other panels that could connect to our board. You said that the the vsync will not be at the middle of the first line of the second field. instead, it will be always be at the start line. Does this have any way to fix in S/W? Or is it there inside the RDK? And how could I know that the vsync is incorrect?

I ever tried to change the signal by setting the I_PN bit in CFG0, but neither mode show the same colorbar in the incorrect color.

Regards,

/ckhsu

Hi Steve:

  Sorry to reply late, I will tried it and reply to you accordingly.

Regards,

/ckhsu