Why the M2 is 1 but the divider is 2 in ADPLLs of AM335x?

Hi Biser,

  Thanks for your reply!

  I can understand your point.

  And you can check the Table 8-17. Output Clocks in Locked Condition, CLKOUT is [M / (N+1)] * CLKINP * [1/M2], and above the table it mentioned, The ADPLLS lock frequency is defined as follows: fDPLL = (M * CLKINP)/(N+1), so I think there is the confusion here, the CLKOUT should be [M / (N+1)] * CLKINP * [1/M2]/2.

  could you help to give the feedback to the related expert to update it to the TRM?

thanks!

Yaoming

thanks!

I have done it.

Thanks yaoming & Biser,  I'm an employee of Tektronix Inc which is one of your customers,  The above-mentioned problem is posted by me, Thanks you two can help me with this.

According to the above discussion, we think the TRM PDF maybe has some error and the correct formulas are:

fDPLL = (M * CLKINP)/(N+1)  ;     CLKOUT =  [M / (N+1)] * CLKINP * [1/M2]/2

But accroding to the conclusion, I can't understand the u-boot SDK Code released for Beaglebone (AM335X) development board.

This is about the MPLL, Core PLL and DDR PLL's setting:

Code: \arch\arm\cpu\armv7\am33xx\board.c 

function call:    s_init()->pll_init();

Code: \arch\arm\cpu\armv7\am33xx\clock.c 

#define OSC                       (V_OSCK/1000000)

/* MAIN PLL    Fdll = 550MHz, 720MHz  or 800MHz */
#define MPUPLL_M_800    800
#define MPUPLL_M_720    720
#define MPUPLL_M_550    550
#define MPUPLL_N            (OSC-1)
#define MPUPLL_M2          1

void pll_init()
{
 /* Start at 550MHz, will be tweaked up if possible. */
 mpu_pll_config(MPUPLL_M_550);
 ...

};

void mpu_pll_config(int mpupll_M)
{
 u32 clkmode, clksel, div_m2;

 clkmode = readl(&cmwkup->clkmoddpllmpu);
 clksel = readl(&cmwkup->clkseldpllmpu);
 div_m2 = readl(&cmwkup->divm2dpllmpu);

 /* Set the PLL to bypass Mode */
 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
  ;

 clksel = clksel & (~CLK_SEL_MASK);
 clksel = clksel | ((mpupll_M << CLK_SEL_SHIFT) | MPUPLL_N);
 writel(clksel, &cmwkup->clkseldpllmpu);

 div_m2 = div_m2 & ~CLK_DIV_MASK;
 div_m2 = div_m2 | MPUPLL_M2;
 writel(div_m2, &cmwkup->divm2dpllmpu);

 clkmode = clkmode | CLK_MODE_SEL;
 writel(clkmode, &cmwkup->clkmoddpllmpu);

 while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
  ;
}

So My question is the frequency "MPUPLL_M_550" we set is FDPLL or  CLKOUT(A8 Clock) ?

On my opinion, the MPUPLL_M_550 should be FDPLL and A8 CLOCK is 550/2 MHz, If we want to set the A8 CLOCK's frequency to be 550MHz, then FDPLL should be  550*2 MHz.

You said your AM335X chip can support the ARM MHz (300~1000), It's the frequency of FDPLL or CLKOUT(A8 CLOCK) ?

Look forward to your reply, Thanks!

there is a typo in the DPLL formula, which should be 2 * (M / (N+1)) * CLKINP (Same as CLKDCOLDO in the diagram).  The formulas in the table are correct.  I will correct this in the TRM.

Regards,

James

Thanks for all of you guys, then the examples and the u-boot code make sense now!