Dear all
We have set register vaule below on dsi.c
r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
r = FLD_MOD(r, 1, 16, 16); /* VP_VSYNC_END */
r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
r = FLD_MOD(r, 1, 18, 18); /* VP_HSYNC_END */
we have 2 question here.
1. we only catch 0x31 on display times . but we have 3 0x21 packet here.
0x01 -> 0x11 -> 0x21 -> 0x21 -> 0x21 -> 0x31 -> (pixel data) -> EOT
2. We haven't seem any Hsync start and Hsync end between Vsync Start and Vsync end
ideal pattern : 0x01 -> 0x21-> 0x31 -> 0x21 -> 0x31-> 0x11
Real Pattern : 0x01 -> 0x11
Please refer pic below.
thank you.
