About C6657 UPP Interrupt setting

ZhengTian Wang

I modify example project 2350.upp_dlb_test that provided by TI employee.The UPP setting in the 2350.upp_dlb_test is polling. Now I revise it as interrupt.But the problem is that the program can't go into UPP_ISR when I run it. I even observe that UPISR(uPP Interrupt Raw Status Register)and UPIER(uPP Interrupt Enabled Status Register) have been set which means the interrupt have been triggered.

So I doubt that it can go into UPP_isr in the loopback mode?

Following is my UPP interrupt setting:

  /***************** interrupt configration for UPP **************************/
  /* open CPINTC0 to map the UPP completetion ISR event to the host interrupt */
  hnd_UPP = CSL_CPINTC_open(2);
  if (hnd_UPP == 0)
  {
   printf ("Error: Unable to open CPINTC-1\n");
   return;
  }
  glbCpintcHnd[2] = (CSL_CPINTC_RegsOvly)hnd_UPP;

  CSL_CPINTC_mapSystemIntrToChannel (hnd_UPP, CSL_INTC0_RPINT, 70);
  CSL_CPINTC_enableSysInterrupt (hnd_UPP, CSL_INTC0_RPINT);
  CSL_CPINTC_enableHostInterrupt (hnd_UPP, 70);
  CSL_CPINTC_enableAllHostInterrupt(hnd_UPP);

vectId = CSL_INTC_VECTID_4;

hIntcUpp= CSL_intcOpen (&intcObjUpp, CSL_GEM_INTC0_OUT_9_PLUS_20_MUL_N, &vectId , NULL);

/* Bind ISR to Interrupt */
gpioHandler.handler = (CSL_IntcEventHandler)&upp_isr;

gpioHandler.arg = 0;

CSL_intcPlugEventHandler(hIntcUpp, &gpioHandler);

  CSL_intcHwControl(hIntcUpp,CSL_INTC_CMD_EVTCLEAR,NULL);
  /* Event Enable */
  CSL_intcHwControl(hIntcUpp, CSL_INTC_CMD_EVTENABLE, NULL);
  /***************** interrupt configration for UPP **************************/

over 12 years ago

0 Steven Ji over 12 years ago

TI__Genius 12065 points

I think the issue might be the mapping of CIC0 output (host interrupt).

It looks like you map the system event (CIC0 input) #156 "CSL_INTC0_RPINT" to CIC0 output "70".

But then you map the CIC0 output "CSL_GEM_INTC0_OUT_9_PLUS_20_MUL_N" to CorePac INTC input.

Number 70 does not correlate with CIC0_OUT(9+20*n), since the output will be either CIC0_OUT(9) for Core0 (n=0) or CIC0_OUT(29) for Core1 (n=1).

You want to try map the CIC0 input to CIC0 output "9" (for CorePac0) or to CIC0 output "29" (for CorePac1), instead of "70" in your test code, if you want to keep the other setting the same.

The following page has some details for the interrupt mechanism for KeyStone devices as well. Hope it helps.

http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices

0 ZhengTian Wang over 12 years ago in reply to Steven Ji

Prodigy 225 points

Mr Ji

Thank you for your reply.

Now I found a new problem.when I observe the UPP register,I found that the transmitter only send 0x200 bytes which should be 0x400,and the receiver got nothing. It didn't trigger any interruption,such as EOLI EOWI EOLQ EOWQ. I puzzled why the result is different from the polling mode when the setting are the same.

/**************************************** UPP init ******************************************/

uppDevParams uPP;

upp_key_config(); // program the KICK0 and 1 registers.
upp_pinmux_enable(); // Though internal loopback, enable uPP in PIN_CONTROL_1

// read PID
int pid = CSL_FEXT(uppRegs->UPPID, UPP_UPPID_REVID);
if(pid != CSL_UPP_UPPID_RESETVAL)
{
printf("\n Error : Incorrect UPP ID read.");
goto upp_test_exit;
}

// toggle SW reset in PCR
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SWRST, RESET);
LOCAL_delay(200);
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SWRST, RUNNING);

CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SOFT, ENABLE);
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_FREE, DISABLE);

// init regs: CTL, ICR, IVR, TCR
uPP = uppDevParams_DEFAULT;
uPP.A.direction = UPP_DIR_XMT;
uPP.A.dataRate = UPP_DR_SDR;
uPP.A.dataWidthVal = dataWidth;
uPP.A.idleValueVal = 0xAAAA;
uPP.A.clkDivVal = 0x1; // use clock div between 0 and 0xF
uPP.A.txThresh = UPP_TT_64B;

uPP.B.direction = UPP_DIR_RCV;
uPP.B.dataRate = UPP_DR_SDR;
uPP.B.dataWidthVal = dataWidth;
uPP.B.idleValueVal = 0xBBBB;
uPP.B.clkDivVal = 0x1;
uPP.B.rcvThresh = UPP_TT_64B;

uPP.loopback = UPP_LB_INTERNAL;
uPP.numChannelsVal = 2;

status = upp_config(&uPP);
if (status < 0)
goto upp_test_exit;

// init interrupt regs

/********************************************** UPP transmit and receive **************************************************/

upp_fill_buffer(xmtBuffer, dataWidth, UPP_DP_RJUST_0FILL, xferSize); // fill transmit buffer with test pattern
upp_fill_buffer(rcvBuffer, 0, UPP_DP_RJUST_0FILL, xferSize); // clear receive buffer
line_cnt = lineCnt;

CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, DISABLE);

// init DMA channels
while(CSL_FEXT(uppRegs->UPQS2, UPP_UPQS2_ACT) == 0)
upp_dma_prog(UPP_DMA_CHAN_Q, (void *)rcvBuffer, line_cnt, byte_cnt, byte_cnt);
while(CSL_FEXT(uppRegs->UPIS2, UPP_UPIS2_ACT) == 0)
upp_dma_prog(UPP_DMA_CHAN_I, (void *)xmtBuffer, line_cnt, byte_cnt, byte_cnt);

// Enable uPP here. PCR.EN bit
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, ENABLE);

line_cnt is 2. byte_cnt is 1024.

0 Steven Ji over 12 years ago in reply to ZhengTian Wang

TI__Genius 12065 points

In the polling mode, which interrupt event you are monitoring please? Is the same event trigger the ISR in the interrupt mode please?

As mentioned in the section 2.6.4 and section 2.8 of uPP user guide, all the uPP events are combined into the single CPU interrupt. So the ISR could be triggered by any event, EOL, EOW or error events.

So maybe you can enable the only event(s) you are interested in first to see if the behavior will the the same as your expectation.

0 ZhengTian Wang over 12 years ago in reply to Steven Ji

Prodigy 225 points

I have solved the problem,and the interrupt is ok.I add two command lines as show below which is the only thing that different from the polling mode.

// CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SOFT, ENABLE);
// CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_FREE, DISABLE);

Now I get a new problem.It is about the function CSL_CPINTC_Handle().

extern CSL_CPINTC_Handle CSL_CPINTC_open (Int32 instNum);

If I set the parameter as 0,it is ok.But when I set it as 1 or 2, it can't go into upp_isr().

So what does the arguement mean? How should I set the parameter?

0 Steven Ji over 12 years ago in reply to ZhengTian Wang

TI__Genius 12065 points

I think the parameter is about the CIC instance number such as CIC_0, CIC_1 or CIC_2.

You should choose CIC_0 since it is the chip level interrupt controller connected to CorePac INTC.

CIC_1 and CIC_2 are connected to EDMA/HyperLink which are not applicable in your case here.

0 ZhengTian Wang over 12 years ago in reply to Steven Ji

Prodigy 225 points

I forgot to mention that I will call this function 3 times in my program.So I am not sure whether I should get 3 instances which means the parameter is 2?

0 Steven Ji over 12 years ago in reply to ZhengTian Wang

TI__Genius 12065 points

I am not sure which PDK/CSL version you are using, but you could find the source file "csl_cpIntcGetBaseAddress.c " in the following location or similar:

C:\ti\pdk_C6657_x_x_x\packages\ti\csl\src\soc\common

The function CSL_CPINTC_Handle CSL_CPINTC_open (Int32 instNum) just returns the handler (base address) of CIC_instNum instance, no matter how many times you call this function.

Hope it could help.

0 ZhengTian Wang over 12 years ago in reply to Steven Ji

Prodigy 225 points

I get it.Thank you!

Is it recommended to use UPP with EDMA? If yes,how should set the destination address UPP_ADR in the transmit mode?

myParamSetupDDR3Read.srcAddr = (Uint32)UPP_TX_DATA;
myParamSetupDDR3Read.aCntbCnt = CSL_EDMA3_CNT_MAKE(144,1);
myParamSetupDDR3Read.dstAddr = (Uint32)UPP_ADR;

Is UPP_ADR 0x02580000?