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AM335x SLEWCTRL bit functionality for McSPI

Magnus Lövdahl
Intellectual 600 points

Hello,

I have a question regarding the SLEWCTRL bit functionality in the Control Module for McSPI. My SPI bus is not working correctly if I set SLEWCTRL bit to 0 (fast) for SPI1_SCLK. It is working just find if I set slow. This worries me a bit since this point to a timing issue. I have gone over the bus a couple of times and I don’t see any wrong settings regarding timing, mode and so on. My question is, what is the difference between fast and slow SLEWCTRL for the SPI1_SCLK pin?

I cannot see any difference on an oscilloscope for the slew when I change it. I have also read that some peripherals do not support slow slew rate. How is it for McSPI?

Best regards

Magnus

  • 0
    TI__Guru 64635 points

    The slew rate control changes the output buffer drive strength during the rise/fall transitions.  I suspect the slew rate is changing at the AM335x terminal or you would not see a difference in SPI1 operation.  You may need to measure the slew rate with a high speed oscilloscope and high speed FET probe as close as possible to the AM335x terminal to see the difference.  If you make this measurement at the far end on the PCB signal trace using low bandwidth equipment, the high frequency portion of the signal transition will be filtered and may not be possible to see the difference.

    I think your problem may be related to a signal integrity issue on the AM335x end of the SPI clock.

    The SPI clock is driven out of the SPI1_SCLK terminal to the external device and is also looped back into the AM335x device via the internal IO buffer.  Therefore, any signal integrity issue on the SPI1_SCLK terminal end of the PCB signal trace can corrupt the clock signal.

    Using the SPI1_SCLK terminal as an input and output simultaneously creates a signal integrity issue at the SPI1_SCLK terminal. The source impedance of the output buffer and transmission line impedance of the circuit board etch creates a voltage divider at the SPI1_SCLK terminal during rising and falling edges of the SPI clock. The voltage at the SPI1_SCLK terminal will change by [VDD * (ZL/(ZL + RS))] when the output buffer toggles and will remain at that voltage until it propagates to the load and the reflection returns. During this time the amplitude of the SPI1_SCLK terminal is close to the switching threshold of the input buffer. Noise may cause the input buffer to generate glitches or invalid transitions of the SPI clock. This will cause problems for the internal SPI logic.

    The figure below is provided to help visualize the circuit topology that creates a voltage divider and resultant voltage waveform.

    This problem can be resolved by placing a series termination resistor between the SPI1_SCLK terminal and the transmission line.  This increases the amplitude of the SPI1_SCLK terminal voltage divider step above the switching threshold so noise will not generate any glitches.  This resistor should always be placed as close as possible to the SPI1_SCLK terminal that is sourcing the SPI clock.  The value recommended for this resistor is between 22 and 50 ohms.  As the resistor value increases the amplitude of the voltage divider step will increase.  However the maximum SPI clock speed will decrease.  The actual value may need to be determined after the circuit board is fabricated.

    Do you have a series termination resistor installed on the AM335x end of the SPI clock?

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 600 points

    Thanks!!

    You right.. We added a resistor between the SPI1_SCLK terminal and the transmission line. It now works.

    Thanks again.

    /Magnus

  • 0 in reply to Magnus Lövdahl
    TI__Expert 7155 points

    I am using a DM8148 SPI as configured as master @ 1.5MHz clock speed. I get bad packet errors at cold temp. As device heats up, the problem disappears. Unfortunately we're unable to add termination resistor to the SPICLK line. The associated PINCNTL[19] bit defaults to 0 (Fast Slew Rate) & the problem exists. However, setting this bit to 1 (Slow Slew Rate), the problem is eliminated.

    The DM8148 errata note below states that the PINCNTL[19] bit should be kept @ its reset default (Fast Slew Rate) state of 0; however, this is the state where the problem occurs.

    So the dilemma is we cannot add series termination resistor to the SPICLK line due to the board layout and if we set the PINCNTL[19] which eliminates the problem, we are opposing the errata note.

    What should we do?

    Advisory 2.1.88 Control Module, Pin Configuration (PINCNTLx): ROM Modifies Bit 19 Revision(s) Affected: 3.0 and earlier

    Work around: To prevent potential datasheet I/O timing violations, software should set bit 19 for all PINCNTLx registers to the reset value defined in the device-specific data manual. Software should also ensure that bit 19 of all PINCNTLx registers is not modified during device operation.

    -Mark