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Question about OpenMP MSMCSRAM (evm6678)

xiaolong liang1
Prodigy 70 points

Other Parts Discussed in Thread: TMS320C6678

hi everyone:

I am very confuse about the  OpenMP memory architecture distribution.

Image_processing is a demo In  MCSDK which MSMCSRAM memory is distributed as the follow:

We can see the MSMCSRAM is distributed in two blocks:MSMCSRAM, MSMCSRAM_NOCACHE. 

From the "TMS320C6678 Data Manual"  the MSMCSRAM address is from 0C000000 to 0C3FFFFF.

Why the MSMCSRAM_NOCACHE address is from 0xa0200000 to 0xa0400000 ?  That address is also out of DDR3 arrange.

So why?

Thanks for your attentions.

  • 0
    Prodigy 70 points

    Seeing the image_processing IPC demo, the MSMCSRAM memory is distributed as the follow:

    As described before the MSMCSRAM address is from 0C000000 to 0C3FFFFF, that accordance with the  "TMS320C6678 Data Manual".

  • 0 in reply to xiaolong liang1
    Prodigy 70 points

    In the "OMP user guide.pdf" we can aslso find information as this:

    • Care must be taken to ensure that platform segments placed in the 0xA0000000 address
    range don’t overlap with platform segments placed in the 'native' (0x0C000000) address
    range.

    /* BAD (overlapping segments) */
    ["MSMCSRAM", {name: "MSMCSRAM", base: 0x0C000000, len:
    0x00200000}],
    ["MSMCSRAM_NOCACHE", {name: "MSMCSRAM_NOCACHE", base: 0xA0100000,
    len: 0x00300000}],

    /* GOOD (no overlapping segments) */

    ["MSMCSRAM", {name: "MSMCSRAM", base: 0x0C000000, len:
    0x00100000}],
    ["MSMCSRAM_NOCACHE", {name: "MSMCSRAM_NOCACHE", base: 0xA0100000,
    len: 0x00300000}],

    That is obviously different with  "TMS320C6678 Data Manual" 's description.

    WHY?

  • 0 in reply to xiaolong liang1
    TI__Mastermind 45025 points

    Hi xiaolong liang1,

    Which version of BIOS, IPC, XDCtools and CCS are you using?

    Are you using the MCSDK?

    Steve

  • 0 in reply to Steven Connell
    Prodigy 70 points

    Steven Connell thanks for your attention,

    The tools version as follow:

    bios_6_34_02_18

    ipc_1_25_00_04

    mcsdk_2_01_02_05

    omp_1_01_03_02

    pdk_C6678_1_1_2_5

    uia_1_01_01_14

    xdais_7_21_01_07

    xdctools_3_24_05_48

    compiler version: c6000_7.4.0


  • 0
    TI__Mastermind 23525 points

    MSMC memory using the native 0x0C000000-0x0C3FFFFF addresses must be cached in L1D, it cannot be disabled.  So if you want an area of MSMC memory not to be cached, you have to use the MPAX registers to remap and access the memory via virtual addresses.  The virtual address was simply mapped to an area outside the DDR and MSMC native areas.  The MAR registers can then disable the caching of the virtual address region.

    Regards,

    Travis