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6670 generic packet 4 Axc



Hi,I use packet mode to transmitte one AXC correctly,but when do in 4 AXC,the first data in my buffer is not in the head of frame and the location is not constant.

In the UG"

In PD, PE common setup, AxC offset window, AxC offset, RadtTC, FrameTC and
FrameMsgTC is not used for generic packet mode. In case of AxC data transfer, we had
to keep correct radio standard timing and AxC data on/off time. If we lose the correct
channel timing, PD (PE) doesn't work for the whole radio frame time. But in case of
generic packet mode, we don't need to keep that correct timing. User program can send
any size of packet at any time they want. PD and PE don't really care the junk duration
between packets and fills empty message during that time. Timestamp field shows
which message has SOP or EOP, so PD easily detect which OBSAI message has valid
data or invalid data."

So ,just use the setup as follows:

for(i=0;i<4;i++)//for(i=0;i<4;i++)
   {//for AxC channel 0 1 2 and 3
   PeCommonSetup.bEnableCh[i] = TRUE;//Enable PE channel for channel 0
   PeCommonSetup.PeDmaCh0[i].bCrcEn =TRUE;// FALSE;//disable CRC for channel 0//例程中为TRUE
   //PeCommonSetup.PeDmaCh0[i].FrameTC = 0;//use framing terminal count 0 for channel 0
   PeCommonSetup.PeDmaCh0[i].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option for channel 0
   PeCommonSetup.PeDmaCh0[i].RtControl = CSL_AIF2_PE_RT_ADD16;//for   second DSP in the chain
   PeCommonSetup.PeDmaCh0[i].CrcType = CSL_AIF2_CRC_16BIT;//CRC type for channel 0

   PeCommonSetup.PeDmaCh0[i].isEthernet = FALSE;//AxC data
   PeCommonSetup.PeDmaCh0[i].CrcObsaiHeader = FALSE;//calculate OBSAI header CRC
   PeCommonSetup.PeInFifo[i].SyncSymbol = 0;//sync symbol offset for channel 0
   PeCommonSetup.PeInFifo[i].MFifoWmark = 3;//Message FIFO water mark for channel 0 

   PeCommonSetup.PeInFifo[i].MFifoFullLevel = 5;//Message FIFO full level for channel 0

   PeCommonSetup.PeChObsaiType[i] =OBSAI_TYPE_GENERIC;// OBSAI_TYPE_LTE;//OBSAI header type for channel 0

   PeCommonSetup.PeChObsaiTS[i] = 2;//0;//OBSAI header Time Stamp for channel 0
   PeCommonSetup.PeChObsaiAddr[i] = i;//OBSAI header address for channel 0
   
   PeCommonSetup.PeChObsaiTsMask[i] = CSL_AIF2_ROUTE_MASK_4LSB;//CSL_AIF2_ROUTE_MASK_NONE;//OBSAI header TS mask for channel 0//
  
   PeCommonSetup.PeChObsaiTsfomat[i] = CSL_AIF2_TSTAMP_FORMAT_GEN_PKT;//CSL_AIF2_TSTAMP_FORMAT_NORM_TS;//OBSAI header TS format for channel 0//
   PeCommonSetup.PeObsaiPkt[i] =TRUE;//FALSE;//Select OBSAI AxC or packet mode  for channel 0//
   PeCommonSetup.PeBbHop[i] = FALSE;//Take OBSAI address from CPPI PS bits  for channel 0
   PeCommonSetup.ChIndex0[i] = i; //channel 0
    PeCommonSetup.bEnableChIndex0[i] = TRUE;

   }

I think the corresponding parameter setting up is the font marked in red.

but ,I made no progress.

Could you tell me why?

  • Hi,

     

    see attached OBSAI generic packet mode example code and hope you can find an answer for yourself.

    Regards,

    /****************************************************************************\
     *           Copyright (C) 2009 Texas Instruments Incorporated.             *
     *                           All Rights Reserved                            *
     *                                                                          *
     * GENERAL DISCLAIMER                                                       *
     * -------------------------------------------------------------------      *
     * All software and related documentation is provided "AS IS" and without   *
     * warranty or support of any kind and Texas Instruments expressly disclaims*
     * all other warranties, express or implied, including, but not limited to, *
     * the implied warranties of merchantability and fitness for a particular   *
     * purpose.  Under no circumstances shall Texas Instruments be liable for   *
     * any incidental, special or consequential damages that result from the    *
     * use or inability to use the software or related documentation, even if   *
     * Texas Instruments has been advised of the liability.                     *
     ****************************************************************************
     *                                                                          *
     * Written by :                                                             *
     *            Albert Bae                                                    *
     *            Texas Instruments                                             *
     *            15 Nov, 2010                                                 *
     *                                                                          *
     ***************************************************************************/
    #include <stdio.h>
    #include <stdlib.h>
    #include <string.h>
    #include <c6x.h>
    #include <ti/csl/src/intc/csl_intc.h>
    
    #include "Aif2_config.h"
    #include "psc_util.h"
    
    /* Define queues for common FDQs */
    #define HOST_TX_COMPLETE_Q     2000
    #define HOST_RX_FDQ            2001
    
    /* These are for the AIF test */
    #define HOST_RX_Q              900
    #define HOST_TX_Q              512
    
    //Users should use 16 bytes aligned data for Aif2 and pkt dma test
    #pragma DATA_ALIGN (host_region, 16)
    Uint8   host_region[64 * 32];//32 64 byte descriptors
    #pragma DATA_ALIGN (buffers, 16)
    Uint8   buffers[32 * 256];
    Uint32  tmp0[8], tmp1[8];
    
    /* Intc variable declarartion */
    CSL_IntcObj    intcObj;
    CSL_IntcHandle   hIntc;
    CSL_IntcEventHandlerRecord  EventHandler[8];
    CSL_IntcGlobalEnableState state;
    
    /* Global structures and variables  */
    CSL_Aif2Obj Aif2Obj;// Aif2 CSL object
    CSL_Aif2Handle hAif2;// Aif2 handle 
    Bool ctrlArg; // Ctrl Argument;
    
    CSL_Aif2Context Aif2Context;//Aif2 context
    CSL_Aif2Param  aif2Param;//AIF2 module specific parameters
    CSL_Status status; // CSL status
       
    CSL_Aif2Setup               aif2Setup;//Aif2 HW setup
    CSL_Aif2LinkSetup           linkSetup;// Setup for links 
    CSL_Aif2GlobalSetup         globalSetup;// global config for AIF2 
    CSL_Aif2CommonSetup         commonSetup; // Setup for common params
       
    CSL_Aif2SdCommonSetup       SdCommonSetup;//SERDES common setup
    CSL_Aif2PdCommonSetup       PdCommonSetup;//PD common setup
    CSL_Aif2PeCommonSetup       PeCommonSetup;//PE common setup
    CSL_Aif2IngrDbSetup         IngrDbSetup;// Ingress data buffer setup 
    CSL_Aif2EgrDbSetup          EgrDbSetup;// Egress data buffer setup 
    CSL_Aif2AdCommonSetup       AdCommonSetup;// Aif2 DMA common setup 
    CSL_Aif2AtCommonSetup       AtCommonSetup; // Aif2 Timer common  setup 
    CSL_Aif2AtEventSetup        AtEventSetup; // Aif2 Timer external and internal event  setup 
    CSL_Aif2AtCountObj          PhyTimerTc;// AT Phy Terminal Count setup
    CSL_Aif2AtCountObj          RadTimerTc;// AT Rad Terminal Count setup
    CSL_Aif2AtCountObj          PhyTimerInit;// AT Phy Init value setup
    CSL_Aif2AtCountObj          RadTimerInit;// AT Rad Init value setup
       
    CSL_Aif2CommonLinkSetup     ComLinkSetup; // Aif2 link common setup 
    CSL_Aif2SdLinkSetup         SdLinkSetup; //SERDES link setup
    CSL_Aif2RmLinkSetup         RmLinkSetup; //RM link setup
    CSL_Aif2TmLinkSetup         TmLinkSetup; //TM link setup
    CSL_Aif2PdLinkSetup         PdLinkSetup; //PD link setup
    CSL_Aif2PeLinkSetup         PeLinkSetup; //PE link setup
    CSL_Aif2RtLinkSetup         RtLinkSetup; //RT link setup
    CSL_Aif2AtLinkSetup         AtLinkSetup; // Aif2 timer link setup (Pi, Delta, PE signal) 
    
    volatile unsigned int int4_result;
    
    interrupt void int4_isr(){
        int i;
        if(int4_result == 1){
          for(i=0;i<8;i++)push_queue(HOST_TX_Q, 1, 0, tmp0[i]);	
        }
        int4_result++;
    
    }
    
    void Intc_config(void)
    {
       CSL_IntcParam    vectId;
       CSL_IntcContext  context;
       //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
       //! GEM0 Intc Configuration              !//
       //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
       /* Setup the global Interrupt */
       context.numEvtEntries = 8;    
       context.eventhandlerRecord = EventHandler; 
       CSL_intcInit(&context);
       /* Enable NMIs  */
       CSL_intcGlobalNmiEnable();
       /* Enable Global Interrupts  */
       CSL_intcGlobalEnable(&state);
       
       /* VectorID for the Global Edma Event  */
       vectId = CSL_INTC_VECTID_4;
       
       /* Opening a handle for the Fsync->EDMA Interrupt Event */                                      
       hIntc   = CSL_intcOpen(&intcObj,
                               AIF2_EVENT7_INTSEL_MAP, // Event 7
                               &vectId,
                               NULL);
       //Hook the ISRs
       CSL_intcHookIsr(vectId,  &int4_isr);
       // Clear the Interrupt    
       CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTCLEAR,  NULL);
       //Enable the Event & the interrupt 
       CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTENABLE,  NULL);
     
    }
    
    void MNavigator_config(void)
    {
        Uint32  flow_a, flow_d, flow_e;
        Uint16  idx;
        MNAV_HostPacketDescriptor *host_pkt;
    
       /* Setup Memory Region 0 for 32 * 64B host descriptors. Our
        * host descriptors will be 64 bytes and it is dividable by 16  */
    
       set_memory_region(0, (Uint32) host_region, 0, 0x00030000);
    
       /*****************************************************************
        * Configure Linking RAM 0 for the descriptor regions.
        */
       set_link_ram(0, QM_LRAM_REGION, 0x3fff); //internal link ram
    
       /* Initialize descriptor regions and buffers */
       memset(host_region, 0, 64 * 32);
       memset(buffers, 0xFF, 256 * 32);
    
        /* Push Host Descriptors to Tx Completion Queue */
        for (idx = 0; idx < 16; idx ++)
        {
          host_pkt = (MNAV_HostPacketDescriptor *)(host_region + (idx * 64));
          host_pkt->type_id = MNAV_DESC_TYPE_HOST;
          host_pkt->pkt_return_qmgr = 0;
          host_pkt->pkt_return_qnum = HOST_TX_COMPLETE_Q;
          host_pkt->return_policy = 1;
          host_pkt->orig_buff0_len = 256;
          host_pkt->orig_buff0_ptr = (Uint32)(buffers + (idx * 256));
          host_pkt->buffer_len = 0;
          host_pkt->buffer_ptr = host_pkt->orig_buff0_ptr;
          host_pkt->next_desc_ptr = NULL;
    
          push_queue(HOST_TX_COMPLETE_Q, 1, 0, (Uint32)(host_pkt));
        }
    
        /* Push Host Descriptors to Rx FDQ */
        for (idx = 16; idx < 32; idx ++)
        {
          host_pkt = (MNAV_HostPacketDescriptor *)(host_region + (idx * 64));
          host_pkt->type_id = MNAV_DESC_TYPE_HOST;
    
          /* Set non-Rx overwrite fields */
          host_pkt->orig_buff0_len = 256;
          host_pkt->orig_buff0_ptr = (Uint32)(buffers + (idx * 256));
          host_pkt->next_desc_ptr = NULL; //don't link Host buffers in Rx FDQ
    
          push_queue(HOST_RX_FDQ, 1, 0, (Uint32)(host_pkt));
        }
    
       /*****************************************************************
        * Configure Rx channel flows
        */
        //Create flow configuration 0 for the Monolithic packets
        flow_a = 0x02000000 | HOST_RX_Q;
        flow_d = (HOST_RX_FDQ << 16) + HOST_RX_FDQ;
        flow_e = flow_d;
        config_rx_flow(AIF_PKTDMA_RX_FLOW_REGION, 0,
                       flow_a, 0, 0, flow_d, flow_e, 0, 0, 0);
    
       /*****************************************************************
        * Enable Tx and Rx channels.
        */
        enable_disable_loopback(0);//disable PktDMA loopback for normal data transfer
        enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 0, 0x80000000);//channel 0
        enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, 0, 0x80000000);//channel 0
    }
    
    void Aif2_MNAV_Obsai_config(void)
    {
       int i;
       /************ Initialize Aif2 structures to avoid unwanted configuration ************************************************/ 
       memset(&globalSetup, 0, sizeof(globalSetup));
       memset(&linkSetup, 0, sizeof(linkSetup));
       memset(&commonSetup, 0, sizeof(commonSetup));
       
       memset(&SdCommonSetup, 0, sizeof(SdCommonSetup));
       memset(&PdCommonSetup, 0, sizeof(PdCommonSetup));
       memset(&PeCommonSetup, 0, sizeof(PeCommonSetup));
       memset(&IngrDbSetup, 0, sizeof(IngrDbSetup));
       memset(&EgrDbSetup, 0, sizeof(EgrDbSetup));
       memset(&AdCommonSetup, 0, sizeof(AdCommonSetup));
       memset(&AtCommonSetup, 0, sizeof(AtCommonSetup));
       memset(&AtEventSetup, 0, sizeof(AtEventSetup));
       memset(&PhyTimerInit, 0, sizeof(PhyTimerInit));
       memset(&RadTimerInit, 0, sizeof(RadTimerInit));
       memset(&PhyTimerTc, 0, sizeof(PhyTimerTc));
       memset(&RadTimerTc, 0, sizeof(RadTimerTc));
       
       memset(&ComLinkSetup, 0, sizeof(ComLinkSetup));
       memset(&SdLinkSetup, 0, sizeof(SdLinkSetup));
       memset(&RmLinkSetup, 0, sizeof(RmLinkSetup));
       memset(&TmLinkSetup, 0, sizeof(TmLinkSetup));
       memset(&PdLinkSetup, 0, sizeof(PdLinkSetup));
       memset(&PeLinkSetup, 0, sizeof(PeLinkSetup));
       memset(&RtLinkSetup, 0, sizeof(RtLinkSetup));
       memset(&AtLinkSetup, 0, sizeof(AtLinkSetup));
        
       // Initialize CSL library, this step is required 
       CSL_aif2Init(&Aif2Context);
       
       // Open Aif2 and get handle 
       hAif2 = CSL_aif2Open(&Aif2Obj, CSL_AIF, &aif2Param, &status);
    
       if ((hAif2 == NULL) || (status != CSL_SOK)) 
       {
          printf ("\nError opening CSL_AIF2");
          exit(1);
       }
       
       /************** populating AIF2 major setup structures ***************************************************/
       aif2Setup.globalSetup = &globalSetup;
       aif2Setup.commonSetup = &commonSetup;
       aif2Setup.linkSetup[CSL_AIF2_LINK_0] = &linkSetup;//assign only one link setup for link 0
     
       // populate global config fields
       globalSetup.ActiveLink[CSL_AIF2_LINK_0] = TRUE;//Activate link 0 for this test
       globalSetup.frameMode = CSL_AIF2_FRAME_MODE_NORMAL; 
      
       //populate common config fields
       commonSetup.pSdCommonSetup = &SdCommonSetup;
       commonSetup.pPdCommonSetup = &PdCommonSetup;
       commonSetup.pPeCommonSetup = &PeCommonSetup;
       commonSetup.pIngrDbSetup   = &IngrDbSetup;
       commonSetup.pEgrDbSetup    = &EgrDbSetup;
       commonSetup.pAdCommonSetup = &AdCommonSetup;
       commonSetup.pAtCommonSetup = &AtCommonSetup;
       commonSetup.pAtEventSetup  = &AtEventSetup; 
       
       /****Link Setup (Do this setup repeatedly with different link setup structure if user wants to use multiple links) ***/
       //populate link config fields for link 0
       linkSetup.linkIndex     = CSL_AIF2_LINK_0; 
       linkSetup.pComLinkSetup = &ComLinkSetup;
       linkSetup.pSdLinkSetup  = &SdLinkSetup;
       linkSetup.pRmLinkSetup  = &RmLinkSetup;
       linkSetup.pTmLinkSetup  = &TmLinkSetup;
       linkSetup.pPdLinkSetup  = &PdLinkSetup;
       linkSetup.pPeLinkSetup  = &PeLinkSetup;
       linkSetup.pRtLinkSetup  = &RtLinkSetup;
       linkSetup.pAtLinkSetup  = &AtLinkSetup;
       
       //Link Common setup
       ComLinkSetup.linkProtocol = CSL_AIF2_LINK_PROTOCOL_OBSAI;
       ComLinkSetup.linkRate = CSL_AIF2_LINK_RATE_4x;
       ComLinkSetup.IngrDataWidth = CSL_AIF2_DATA_WIDTH_16_BIT;
       ComLinkSetup.EgrDataWidth = CSL_AIF2_DATA_WIDTH_16_BIT;
       
       //SD link setup
       SdLinkSetup.rxAlign = CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE;
       SdLinkSetup.rxLos = CSL_AIF2_SD_RX_LOS_ENABLE;
       SdLinkSetup.rxCdrAlgorithm = CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_17;
       SdLinkSetup.rxInvertPolarity = CSL_AIF2_SD_RX_NORMAL_POLARITY;
       SdLinkSetup.rxTermination = CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 ;//for AC coupled application
       SdLinkSetup.rxEqualizerConfig = CSL_AIF2_SD_RX_EQ_ADAPTIVE;//Equalizer On
       SdLinkSetup.bRxEqHold = FALSE;//fixed value
       SdLinkSetup.bRxOffsetComp = TRUE;//fixed value
       SdLinkSetup.bEnableTxSyncMater = TRUE; //fixed value
       SdLinkSetup.txInvertPolarity = CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY;
       SdLinkSetup.txOutputSwing = CSL_AIF2_SD_TX_OUTPUT_SWING_14;
       SdLinkSetup.txPrecursorTapWeight = CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2;// -5%
       SdLinkSetup.txPostcursorTapWeight = CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24;// -20%
       SdLinkSetup.bTxFirFilterUpdate = TRUE;//FIR filter update on
       
       //TM link setup
       TmLinkSetup.bEnableTmLink = TRUE;
       TmLinkSetup.bEnableRmLos = FALSE;
       TmLinkSetup.SeedValue = 0x1;
       TmLinkSetup.bEnableScrambler = FALSE;
       
       //RM link setup
       RmLinkSetup.bEnableRmLink = TRUE;
       RmLinkSetup.RmFifoThold = CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY;
       RmLinkSetup.RmErrorSuppress = CSL_AIF2_RM_ERROR_ALLOW;
       RmLinkSetup.bEnableSdAutoAlign = FALSE;
       RmLinkSetup.bEnableScrambler = FALSE;
       RmLinkSetup.bEnableLcvUnsync = FALSE;
       RmLinkSetup.bEnableLcvControl = FALSE;
       RmLinkSetup.bEnableWatchDog = FALSE;
       RmLinkSetup.WatchDogWrap = 0xFF;//set watch dog wrap value
       RmLinkSetup.bEnableClockQuality = FALSE;
       RmLinkSetup.ClockMonitorWrap = 0;
       RmLinkSetup.losDetThreshold = RM_LOS_DET_THOLD;
       RmLinkSetup.SyncThreshold = RM_SYNC_THOLD;
       RmLinkSetup.FrameSyncThreshold = RM_SYNC_THOLD;
       RmLinkSetup.UnsyncThreshold = RM_UNSYNC_THOLD;
       RmLinkSetup.FrameUnsyncThreshold = RM_UNSYNC_THOLD;
       
       //RT link setup
       RtLinkSetup.CiSelect =  CSL_AIF2_LINK_0;
       RtLinkSetup.bEnableEmptyMsg = TRUE;
       RtLinkSetup.RtConfig = CSL_AIF2_RT_MODE_TRANSMIT;// takes PE input only
       
       //PD link setup
       PdLinkSetup.bEnablePdLink = TRUE;
       PdLinkSetup.Crc8Poly = CRC8_POLY;
       PdLinkSetup.Crc8Seed = CRC8_SEED;
       PdLinkSetup.PdTypeLut[OBSAI_TYPE_GENERIC].ObsaiTsFormat = CSL_AIF2_TSTAMP_FORMAT_GEN_PKT;
       PdLinkSetup.PdTypeLut[OBSAI_TYPE_GENERIC].PdCrcType = CSL_AIF2_CRC_16BIT;
       PdLinkSetup.PdTypeLut[OBSAI_TYPE_GENERIC].bEnableCrc = FALSE;
       PdLinkSetup.PdTypeLut[OBSAI_TYPE_GENERIC].PdObsaiMode = CSL_AIF2_PD_DATA_PKT;
       PdLinkSetup.PdTypeLut[OBSAI_TYPE_GENERIC].bEnableEnetStrip = FALSE;
       PdLinkSetup.PdTypeLut[OBSAI_TYPE_GENERIC].bEnableCrcHeader = FALSE;
       
       //PE link setup
       PeLinkSetup.bEnablePeLink = TRUE;
       PeLinkSetup.PeCppiDioSel = CSL_AIF2_CPPI;
       PeLinkSetup.TddAxc = FALSE;
       PeLinkSetup.bEnObsaiBubbleBW = FALSE;
       PeLinkSetup.PeDelay = DB_PE_DELAY_OBSAI;//28 sys_clks delay between DB and PE for OBSAI
       PeLinkSetup.Crc8Poly = CRC8_POLY;
       PeLinkSetup.Crc8Seed = CRC8_SEED;
       
       //AT link setup
       AtLinkSetup.PE1Offset = 300;
       AtLinkSetup.PE2Offset = 310;
       AtLinkSetup.DeltaOffset = 370;// Packet DMA delay + pe1 + pe2 = 300 + 10 + 60 (min Delta)
       AtLinkSetup.PiMin = 370;
       AtLinkSetup.PiMax = 390;
       AtLinkSetup.IsNegativeDelta = FALSE;//positive delta
       
       /************** Common Setup ********************************************************************************/
       //SD common setup
       SdCommonSetup.bEnablePllB8 = TRUE;
       SdCommonSetup.CLKBYP_B8 = CSL_AIF2_PLL_CLOCK_NO_BYPASS;
       SdCommonSetup.LB_B8 = CSL_AIF2_PLL_LOOP_BAND_MID;//High BW is also fine
       SdCommonSetup.VoltRangeB8 = CSL_AIF2_PLL_VOLTAGE_LOW;//fixed factor
       SdCommonSetup.SleepPllB8 = CSL_AIF2_PLL_AWAKE;
       SdCommonSetup.pllMpyFactorB8 = CSL_AIF2_PLL_MUL_FACTOR_25X;//for OBSAI when reference clock is 122.88 Mhz
       SdCommonSetup.SysClockSelect = CSL_AIF2_SD_BYTECLOCK_FROM_B8;
       SdCommonSetup.DisableLinkClock[0] = FALSE;//enable link0 clock
       
       
       //PD common setup
       PdCommonSetup.PdCppiDioSel = CSL_AIF2_CPPI;//AxC data uses CPPI for DMA machine
       
       PdCommonSetup.PdRoute[0].RouteTs = 0x0;//Route OBSAI time stamp for channel 0
       PdCommonSetup.PdRoute[0].RouteType = OBSAI_TYPE_GENERIC;//Route OBSAI type for channel 0
       PdCommonSetup.PdRoute[0].RouteAddr = 0;//Route OBSAI address for channel 0
       PdCommonSetup.PdRoute[0].RouteLink = CSL_AIF2_LINK_0;//Route link for channel 0
       PdCommonSetup.PdRoute[0].RouteMask = CSL_AIF2_ROUTE_MASK_4LSB;//Route TS mask for channel 0
       PdCommonSetup.PdChConfig[0].bChannelEn = TRUE;//Channel enable for channel 0
       PdCommonSetup.PdChConfig[0].DataFormat = CSL_AIF2_LINK_DATA_TYPE_NORMAL;//Data format for channel 0
       
       PdCommonSetup.PdChConfig1[0].bTsWatchDogEn = FALSE;//disable watchdog for channel 0
       PdCommonSetup.PdChConfig1[0].DataFormat = CSL_AIF2_GSM_DATA_OTHER;//Non GSM data
       PdCommonSetup.PdChConfig1[0].TddEnable = 0xFFFF;//PD TDD, enables all symbols(FDD) for channel 0 
       PdCommonSetup.TddEnable1[0] = 0xFFFFFFFF;//enables all symbols(FDD)
       PdCommonSetup.TddEnable2[0] = 0xFFFFFFFF;//enables all symbols(FDD)
       PdCommonSetup.TddEnable3[0] = 0xFFFFFFFF;//enables all symbols(FDD)
       PdCommonSetup.TddEnable4[0] = 0xFFFFFFFF;//enables all symbols(FDD)
       
       //PE common setup
       PeCommonSetup.PeTokenPhase = 0;
       PeCommonSetup.EnetHeaderSelect = 0;//bit order for Ethernet preamble and SOF 
       
       PeCommonSetup.bEnableCh[0] = TRUE;//Enable PE channel for channel 0
       PeCommonSetup.PeDmaCh0[0].bCrcEn = FALSE;//disable CRC for channel 0
       PeCommonSetup.PeDmaCh0[0].FrameTC = 0;//use framing terminal count 0 for channel 0
       PeCommonSetup.PeDmaCh0[0].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option for channel 0
       PeCommonSetup.PeDmaCh0[0].CrcType = CSL_AIF2_CRC_16BIT;//CRC type for channel 0
       PeCommonSetup.PeDmaCh0[0].isEthernet = FALSE;//AxC data 
       PeCommonSetup.PeDmaCh0[0].CrcObsaiHeader = FALSE;//calculate OBSAI header CRC
       PeCommonSetup.PeInFifo[0].SyncSymbol = 0;//sync symbol offset for channel 0
       PeCommonSetup.PeInFifo[0].MFifoWmark = 2;//Message FIFO water mark for channel 0
       PeCommonSetup.PeInFifo[0].MFifoFullLevel = 3;//Message FIFO full level for channel 0
       
       PeCommonSetup.PeModuloTc[0].bEnableRule = TRUE;
       PeCommonSetup.PeModuloTc[0].RuleModulo = 0;//Setup modulo rule 0 Modulo
       PeCommonSetup.PeModuloTc[0].bRuleObsaiCtlMsg = FALSE;
       PeCommonSetup.PeModuloTc[0].RuleIndex = 0;//Setup modulo rule 0 index
       PeCommonSetup.PeModuloTc[0].RuleLink = CSL_AIF2_LINK_0;//Route egress modulo rule 0 to link 0
       
       PeCommonSetup.PeChObsaiType[0] = OBSAI_TYPE_GENERIC;//OBSAI header type for channel 0
       PeCommonSetup.PeChObsaiTS[0] = 0x0;//OBSAI header Time Stamp for channel 0
       PeCommonSetup.PeChObsaiAddr[0] = 0;//OBSAI header address for channel 0
       PeCommonSetup.PeChObsaiTsMask[0] = CSL_AIF2_ROUTE_MASK_4LSB;//OBSAI header TS mask for channel 0
       PeCommonSetup.PeChObsaiTsfomat[0] = CSL_AIF2_TSTAMP_FORMAT_GEN_PKT;//OBSAI header TS format for channel 0
       PeCommonSetup.PeObsaiPkt[0] = TRUE;//Select OBSAI packet mode  for channel 0
       PeCommonSetup.PeBbHop[0] = FALSE;//Take OBSAI address from CPPI PS bits  for channel 0
       
       //Dual bit map setup. 
       PeCommonSetup.PeObsaiDualBitMap[0].DbmX = 0;//set X-1. use Max BW for one channel
       PeCommonSetup.PeObsaiDualBitMap[0].DbmXBubble = 0;
       PeCommonSetup.PeObsaiDualBitMap[0].Dbm1Mult = 0;//set n-1
       PeCommonSetup.PeObsaiDualBitMap[0].Dbm1Size = 0;//set n-1
       PeCommonSetup.PeObsaiDualBitMap[0].Dbm1Map[0] = 0x0;
       
       PeCommonSetup.ChIndex0[0] = 0; //channel 0
       PeCommonSetup.bEnableChIndex0[0] = TRUE;//Route egress channel 0 to modulo rule 0
       
       //Ingress DB setup
       IngrDbSetup.bEnableIngrDb = TRUE; //Enable Ingress DB
       IngrDbSetup.bEnableChannel[0] = TRUE; //Enable Ingress DB channel 0
       IngrDbSetup.IngrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0; //Set DB FIFO base address for channel 0
       IngrDbSetup.IngrDbChannel[0].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW128; //Set DB FIFO depth for channel 0 
       IngrDbSetup.IngrDbChannel[0].DataSwap = CSL_AIF2_DB_WORD_SWAP; //DL
       IngrDbSetup.IngrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
       IngrDbSetup.IngrDbChannel[0].bEnablePsData = FALSE; //Enable 4 bytes PS data
       IngrDbSetup.IngrDbChannel[0].PacketType = 0; //User data
       
       //Egress DB setup
       EgrDbSetup.bEnableEgrDb = TRUE; //Enable Ingress DB
       EgrDbSetup.PmControl = CSL_AIF2_DB_PM_TOKEN_FIFO;//for normal packet performance
       EgrDbSetup.bEnableChannel[0] = TRUE; //Enable Egress DB channel 0
       EgrDbSetup.EgrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0; //Set DB FIFO base address for channel 0
       EgrDbSetup.EgrDbChannel[0].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW128; //Set DB FIFO depth for channel 0
       EgrDbSetup.EgrDbChannel[0].DataSwap = CSL_AIF2_DB_WORD_SWAP; //DL
       EgrDbSetup.EgrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
       
       //AD Common setup
       AdCommonSetup.IngrGlobalEnable = TRUE;
       AdCommonSetup.EgrGlobalEnable = TRUE;
       AdCommonSetup.FailMode = CSL_AIF2_AD_DROP;//drop fail packet
       AdCommonSetup.IngrPriority = CSL_AIF2_AD_PKT_PRI;
       AdCommonSetup.EgrPriority = CSL_AIF2_AD_NON_AXC_PRI;
       AdCommonSetup.Tx_QueNum = AIF2_BASE_TX_QUE_NUM;//base egress queue number setup to 512
       
       //AT Common setup
       AtCommonSetup.PhySyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Phy timer trigger
       AtCommonSetup.RadSyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Rad timer trigger
       AtCommonSetup.SyncMode = CSL_AIF2_NON_RP1_MODE;
       AtCommonSetup.AutoResyncMode = CSL_AIF2_AUTO_RESYNC_MODE;
       AtCommonSetup.CrcMode = CSL_AIF2_AT_CRC_DONT_USE;//Do not use RP1 CRC in this test
       AtCommonSetup.PhytCompValue = 0;
       
       AtCommonSetup.AtInit.pPhyTimerInit = &PhyTimerInit;
       AtCommonSetup.AtInit.pRadTimerInit = &RadTimerInit;
       PhyTimerInit.ClockNum = 0;
       PhyTimerInit.FrameLsbNum = 0;
       PhyTimerInit.FrameMsbNum = 0;
       RadTimerInit.ClockNum = 0;
       RadTimerInit.SymbolNum = 0;
       RadTimerInit.FrameLsbNum = 0;
       RadTimerInit.FrameMsbNum = 0;
       AtCommonSetup.AtTerminalCount.pPhyTimerTc = &PhyTimerTc;
       AtCommonSetup.AtTerminalCount.pRadTimerTc = &RadTimerTc;
       PhyTimerTc.FrameLsbNum = FRAME_COUNT_TC_PHY_TIMER;//set phy Frame TC to 4095
       PhyTimerTc.ClockNum = CLOCK_COUNT_TC_PHY_TIMER; //set phy clock TC to 3071999
       RadTimerTc.FrameLsbNum = FRAME_COUNT_TC_LTE_FDD;//set Frame TC to 4095
       RadTimerTc.SymbolNum = SYMBOL_COUNT_TC_LTE_FDD; //set Symbol TC to 9
       RadTimerTc.LutIndexNum = 0; //set LutIndex TC to 0
       AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = CLOCK_COUNT_TC_LTE_FDD;//set Clock count TC to 307199
      
       //AT Event setup (Event 7)
       AtEventSetup.AtRadEvent[7].EventSelect = CSL_AIF2_EVENT_7;//Select Event 7 
       AtEventSetup.AtRadEvent[7].EventOffset = 400; 
       AtEventSetup.AtRadEvent[7].EvtStrobeSel = CSL_AIF2_RADT_FRAME; 
       AtEventSetup.AtRadEvent[7].EventModulo = 3071999; 
       AtEventSetup.AtRadEvent[7].EventMaskLsb = 0xFFFFFFFF; 
       AtEventSetup.AtRadEvent[7].EventMaskMsb = 0xFFFFFFFF; 
       AtEventSetup.bEnableRadEvent[7] = TRUE;//Enable Event 7
       
       /****** Do AIF2 HW setup (set all MMRs above) **********************************************************************/
       CSL_aif2HwSetup(hAif2, &aif2Setup);
    
       ctrlArg = TRUE;
       hAif2->arg_link = CSL_AIF2_LINK_0;//Select link num
       
       //Enable Serdes loopback for link 0
       CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg);
       //Enable Tx/Rx of link 0
       CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
       CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);
       for(i=0;i<100;i++)asm (" NOP 9 ");//insert time delay for aif2 configuration completion 
       
       //AT Arm timer
       CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_ARM_TIMER, (void *)&ctrlArg);
       
       //Trigger the SW debug frame sync
       CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DEBUG_SYNC, (void *)&ctrlArg);
    
    }
    
    void main(void)
    {
        Uint32  hostRxCount;
        Uint16  testpass;
        Uint32 *temp;
        Uint32  idx, idx2, rx_count, value;
        MNAV_HostPacketDescriptor *host_pkt;
       
        printf("Beginning AIF2 OBSAI Generic packet  test:\n\n");
        for(idx=0;idx<1000;idx++)asm (" NOP 9 ");//delay for printf not to block ISR execution
    
        enable_module(aif_pdctl, aif_mdctl);//Enable AIF2 module power
    
        int4_result = 0;
        
        Intc_config();
        
        MNavigator_config();//multicore navigator configuration for LTE
        
        for(idx =0; idx < 8; idx++){  //push 8 host linked packets into Tx queue for test
    
        //Create Host packet Tx descriptor #2 with 2 linked Host Buf desc.
        tmp0[idx] = pop_queue(HOST_TX_COMPLETE_Q);
        tmp0[idx] &= 0xFFFFFFF0;//set DESC_SIZE field to zero
        tmp1[idx] = pop_queue(HOST_TX_COMPLETE_Q);
        tmp1[idx] &= 0xFFFFFFF0;//set DESC_SIZE field to zero
        
        host_pkt = (MNAV_HostPacketDescriptor *)tmp0[idx];
    
        host_pkt->ps_reg_loc = 1;
        host_pkt->return_policy = 1; 
        host_pkt->psv_word_count = 0;
        host_pkt->buffer_len = 256;
        host_pkt->packet_length = 256 * 2 ;
        host_pkt->next_desc_ptr = tmp1[idx];
        host_pkt->src_tag_lo = 0; //should be matched with Rx flow id
    
        temp = (Uint32 *)host_pkt->buffer_ptr;
        for (idx2 = 0; idx2 < 64; idx2 ++) temp[idx2] = idx2 + 0x10000;
    
        host_pkt = (MNAV_HostPacketDescriptor *)tmp1[idx];
        host_pkt->buffer_len = 256;
        host_pkt->next_desc_ptr = NULL;
    
        temp = (Uint32 *)host_pkt->buffer_ptr;
        for (idx2 = 0; idx2 < 64; idx2 ++) temp[idx2] = idx2 + 0x20000;
       
        tmp0[idx] |= 0x00000003;//set DESC_SIZE to 3 for 64 byte host descriptors
        tmp1[idx] |= 0x00000003;//set DESC_SIZE to 3 for 64 byte host descriptors
        //Tx decriptors will be pushed in ISR for this example
        }
        
        Aif2_MNAV_Obsai_config();//Aif2 configuration for M Navigator mode
    
         /*****************************************************************
        * Enable AIF2 and wait for completion.
        */
        while(1)
        {
            asm (" NOP 9 ");
            asm (" NOP 9 ");
            if(int4_result == 3)//Wait two phy frame time
            {
                //AT disable all events and halt timer
                ctrlArg = TRUE;
    	     CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS, (void *)&ctrlArg);
                CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_HALT_TIMER, (void *)&ctrlArg);
    	     ctrlArg = FALSE;//disable AD scheduler and Rx, Tx Link
    	     CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg);
                CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg);
    	     CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
                CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);
                CSL_aif2Reset(hAif2);//reset all aif2 modules 
                break;
            }
        }
    
        hostRxCount = 0;  // descriptor count for host RX queue
        while (hostRxCount < 8)
        {
            // Get current descriptor count for host RX queue
            hostRxCount = get_descriptor_count(HOST_RX_Q);
            if (hostRxCount != 0)
            printf(" Number of monolithic packets received in RX queue: %d\n", hostRxCount);
        }
    
       /*****************************************************************
        * Compare the data in the destination buffers.
        */
    
        /* Compare the Monolithic packet data */
        testpass = 1;
        rx_count = get_descriptor_count(HOST_RX_Q);
    
        for (idx = 0; idx < rx_count; idx ++)
        {
          tmp0[idx] = pop_queue(HOST_RX_Q);
          host_pkt = (MNAV_HostPacketDescriptor *)tmp0[idx];
          temp = (Uint32 *)host_pkt->buffer_ptr;
          for (idx2 = 0; idx2 < 64; idx2 ++)if (temp[idx2] != (idx2 + 0x10000)) testpass = 0;
    	  
          tmp1[idx] = host_pkt->next_desc_ptr;
          host_pkt = (MNAV_HostPacketDescriptor *)tmp1[idx];
          temp = (Uint32 *)host_pkt->buffer_ptr;
          for (idx2 = 0; idx2 < 64; idx2 ++)if (temp[idx2] != (idx2 + 0x20000)) testpass = 0;
    	  
          push_queue(HOST_RX_FDQ, 1, 0, tmp0[idx]);
          push_queue(HOST_RX_FDQ, 1, 0, tmp1[idx]);
        }
    
        if (testpass == 1)
          printf(" Test a) Host Packet Data Send/Recv: PASS\n");
        else
          printf(" Test a) Host Packet Data Send/Recv: FAIL\n");
    
    
        /* read the descriptor counts of the Host queues. */
        value = get_descriptor_count(HOST_TX_Q);
        if (value != 0) printf(" Test b1) Host Packet Tx Descriptor Counts:%d FAIL\n",value);
        else printf(" Test b1) Host Packet Tx Descriptor Counts:%d PASS\n",value);
    
        value = get_descriptor_count(HOST_TX_COMPLETE_Q);
        if (value != 16) printf(" Test b2) Host Packet Tx Complete Descriptor Counts:%d FAIL\n",value);
        else printf(" Test b2) Host Packet Tx Complete Descriptor Counts:%d PASS\n",value);
    
        value = get_descriptor_count(HOST_RX_Q);
        if (value != 0) printf(" Test b3) Host Packet Rx Descriptor Counts:%d FAIL\n",value);
        else printf(" Test b3) Host Packet Rx Descriptor Counts:%d PASS\n",value);
        
        value = get_descriptor_count(HOST_RX_FDQ);
        if (value != 16) printf(" Test b4) Host Packet Rx Free Descriptor Counts:%d FAIL\n",value);
        else printf(" Test b4) Host Packet Rx Free Descriptor Counts:%d PASS\n",value);
    
        printf("\nEnding AIF2 OBSAI Generic packet  test\n");
        
    }
    
    7217.Aif2_config.h

    Albert