Team,
Could you please help with the below questions:
- Looking at the C6657 EVM the smartreflex is handled via a UCD9222. It seems that there VIDx pins from the C665x go through an FPGA before it reaches the UCD9222.
Is there a specific reason why a FPGA is used in between (like power sequencing, silicon issue, ...etc)?
- Looking at section 5 of SPRABI2B. The information primelarly focus on C667x. In the case of using UCD9222 for C665x are there some special care to take that is not mentioned in the SPRABI2B?
I think that example 1 at page 50 is the closest scenario to use for C665x and that the EVM does implement a comparable design (with only 1 UCD92xx port used). Correct?
- Looking at the below page there seem as well a solution based on LM10010:
http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=149653
What is the advantage of such solution (like cost, board space, more power optimized for C665x, .etc) over using UCD9222?
Would the typical application circuit at page 10 of SNVS717C fit for C6657?
Are there some more specific PCB layout information specifically for LM10010 like bulk and decoupling capacitors values/placement, ..etc?
Thanks and best reagrds,
Anthony
