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DM3730 SPI Master Receive only mode

Sujith Varghese
Prodigy 60 points

How to check  whether new data is available in Rx register ,when SPI master is in receive only mode?

  • 0
    TI__Guru 65405 points

    Hi Sujith,

    In the master receive-only mode, software must write dummy data to the MCSPI_TXx register, and only after the TX buffer is empty (check the MCSPI_CH0STAT[2] bit in the software). Only one dummy write is enough to receive any number of words from the slave. Software should ensure that the MCSPI_TXx register is always full (the TXx_EMPTY bits of SPIm.MCSPI_IRQSTATUS) when receiving. The content of the MCSPI_TXx register is always loaded into the shift register when the shift register is assigned. After writing the dummy data to the MCSPI_TXx register, the TXx_EMPTY and TXx_UNDERFLOW bits in the SPIm.MCSPI_IRQSTATUS register are never set in receive-only mode.

    For more details refer to TRM section 20.5.2.4 Master Receive-Only Mode (Half Duplex)

    http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 60 points

    HI Cvetolin,

    I need a clarity on this statement "Software should ensure that the MCSPI_TXx register is always full (the TXx_EMPTY bits of SPIm.MCSPI_IRQSTATUS) when receiving".

    I am not enabling Interrupt , I am using polling method for status check. When i continuously check the status bit i observe that The RXS bit in the Status register is always full and TXS register is always empty .

    When i try to read the Receive register based on the RXS bit full condition,I seen that Receive register is not updated.