pcie flow control

hello
      I'm using the dm8168 as a root complex.The DM8168 and a FPGA are connected by a pcie(V2.0).As a master device,the DM8168 is writing a frame(1920*1080p60) of image data to FPGA through pcie.But,the rate of pcie is faster than 2.5Gbps ,and the FPGA processing speed is only 256Mbit clock.Half of one frame(1920*1080p60) of image data will be lost by detecting.So,could i configure the pcie flow control in some register or other place when i receive a freedback command from  FPGA,such the Lane Skew Register->FC_DISABLE or other register?If I can ,how can I config it and which place receive this order in the pcie protocol?