C6713 interfacing a DAC for AWG

Brady,

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

First, you have to look at the interfaces that are available on the C6713 (see the datasheet), and probably those specific to the 5-6K board. The 5-6K board has a parallel interface that gives you access to the C6713's parallel EMIF bus, and it has two (2) serial interfaces to the C6713's serial McBSP ports. You will want to pull up the McBSP User's Guide to understand the serial formats that the McBSP is compatible with.

Second, you will want to go to TI.com and find the DAC products, in particular the Selection Guide. There you can put in your required sampling frequency, number of bits of resolution, and the types of interfaces that you can use with the C6713. That will tell you which ones can work.

Third, you will need to get an estimate of the number of DSP cycles you will need to use per sample as a first approximation of the processing requirements.

For example, the C6713 can run up to 225 MHz which means it can execute up to 225 instruction cycles at a 1MHz sample rate, but you may need to deal with the Nyquist sampling rate for your signals and a reasonable margin above that. If you decide to sample at 5x the center frequency, that would give you 45 instruction cycles per 5MHz sample.

The McBSP serial ports will have a maximum clock rate which equals their maximum bit rate. If that maximum were 40MHz, then you could theoretically write 8 bits x 5MHz. But implementing a maximum speed McBSP through the buffers and across the connectors of the 5-6K board might be a challenge. I tend to be pretty conservative and would not want to run an interface like that near the maximum speed. So the McBSP would be a tough design challenge.

The EMIF can run at a higher clock rate and it moves more bits per clock cycle than the McBSP does. It will take several EMIF clock cycles per sample, but it is going to be much easier to reach the 5MHz rate than the McBSP, in my opinion. You will need to look at the timing in the EMIF User's Guide and the parallel interface timing requirements of any DAC that you find that fits your requirements.

Search TI.com, the E2E forums, the TI Wiki Pages, and the web for WBFM algorithms to get an idea of how much processing you will need to do. It could be as trivial as writing samples from a set of tables to generate your chirps, or you may have an input stream of data that dictates what your outputs need to be. There is a big difference in processing requirements for the different algorithms that you might require for your project.

Check out the TI.com items that I mention, look through the documents, and search the online resources. Then you can start applying your engineering skills to deciding the feasibility and requirements to implement your project.

Please describe what you find, let us know if you are unable to locate some items (and what you tried to get them), and ask any specific questions that come up from your search. You may also want to post specific requirements to the Data Converters Forum on E2E.

Regards,
RandyP

Hi Brady,

TI offers a wide range of ADC/DAC with different sampling rates. please refer to http://www.ti.com/lsds/ti/analog/dataconverters/adc_dac_quick_search.page to check for compatibilty.

You may also find the "TMS320C6713 Hardware Designer’s Resource Guide" useful.

Regards,

Shankari.

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