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DM368 PLL2 clock frequency

Chee Wooi Cheok
Prodigy 190 points

DM368-432 PLL2 = 432MHz for 24-MHz Input Crystal example (stated in data sheet sprs668c).

DM365-300 PLL2 = 594MHz for the same 24-MHz Input Crystal example (stated in data sheet sprs457e).

Similarly DM365-270 PLL2 = 270MHz but DM365-216 PLL2 = 432MHz.

Since the ARM clock is derived from the PLL2 controller, may I know why higher ARM clock frequency requires lower PLL2 clock frequency?

Kindly enlighten.

Regards

  • 0
    Guru 31670 points

    Hi Chee,

    Have you taken into account of all the SYSCLK divisor values? 

  • 0 in reply to Renjith Thomas
    Prodigy 190 points

     

    and for higher ARM clock frequency of 297MHz, PLL2 is set at 594MHz (PLL2 frequency is double ARM clock frequency)

    PLL2 frequency can be set to 297MHz with 2M/(N+1) = 198/16

     

  • 0 in reply to Chee Wooi Cheok
    Prodigy 190 points

    Sorry to re-post due to the previous post is being truncated

    Kindly refer to sprs457 pg 60 on 24MHz Input crystal example:

     

    My question is why for ARM clock frequency of 270MHz, PLL2 is set at 270MHz as well (PLL2 frequency = ARM clock frequency)

    but for lower ARM clock frequency of 216MHz, PLL2 is set at 432MHz (PLL2 frequency is double ARM clock frequency)

    where the PLL2 frequency can be set to 216MHz as well with 2M/(N+1) = 18/2  

    and for higher ARM clock frequency of 297MHz, PLL2 is set at 594MHz (PLL2 frequency is double ARM clock frequency)

    PLL2 frequency can be set to 297MHz with 2M/(N+1) = 198/16

     

    Kindly enlighten is there any specific reason of doing that?  

    p/s: just for information that for DM368 with ARM clock frequency of 432MHz, the PLL2 frequency is set to 432MHz, not double the ARM clock frequency.   

  • 0 in reply to Chee Wooi Cheok
    Guru 31670 points

    Chee,

    Your question is very good and logical :)

    The tables are just provided as examples, as its not mandatory to follow. This is very obvious if you go through the Note 1 & 2 given just above the table. Also please note that ARM can take clock from PLL1->SYSCLK2 as well.

    Chee Wooi Cheok said:
    just for information that for DM368 with ARM clock frequency of 432MHz, the PLL2 frequency is set to 432MHz, not double the ARM clock frequency

    I think why doubling the frequency for 432MHz is not done is to avoid reaching the peak which the silicon can handle. But I have tried quite higher multipliers for PLL on DM36x before and it was working fine. Also please note that, in the UBL source code, these values are not really used.