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About configuration of AM335x GPMC

g.f.
Guru 15520 points

Hi,

I have a question about AM335x GPMC.

I'm trying to reconfigure GPMC CS0 during XIP boot.
In ROM code it setup CS0 size to 16MB, so I want to change it to 64MB.
And also want to reconfigure the timing.

I read TRM(spruh73h)page.264 and I understand that it's not allowed to
reconfigure if there is ongoing access to CS0.
So, I will make code which configure CS0 and load from NOR Flash to IRAM using CPU.
After loading the code to IRAM, it will execute the CS0 configuration.
But I don't know how to detect the loading is done and detect that there is no ongoing access.

Is there any method to detect that there is no ongoing access to the CS?

best regards,
g.f.

  • 0
    TI__Guru**** 393215 points
    Hi g.f,
     
    I'm not a software expert, but I think the MLO is executed from internal RAM. So you could try and squeeze your reconfiguration code into it.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points
    Sorry, just realized that you are talking about XIP, and what I suggested isn't quite true. But you could try and load the reconfiguration code into internal RAM and pass execution to it.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points

    Hi Biser,

    Thank you for the response.

    I uderstand but let me check again.
    Do you mean it's not necessary to detect that loading the code is done
    before executing the configuration of CS0?
    Is there any method to detect that there is no ongoing accsss to CS0?

    By the way, Is it correct that ROM code configurate CS0 size to 16MB
    when XIP boot is selected?

    best regards,
    g.f.

  • 0 in reply to g.f.
    TI__Guru**** 393215 points
    I meant that you should try to reconfigure the GPMC very early in the boot process. I imagine that this will have to be a small subroutine that's loaded into internal RAM by the MLO and then started from there. When it finishes GPMC reconfiguration it should pass execution back to the MLO - something like that.
     
    The ROM code for this device isn't public, but for XIP devices it configures only addresses A0 - A11, so at least pinmux configuration is necessary early in the boot code.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points

    Hi Biser,

    Sorry I'm troubling you.

    I will reconfigure GPMC CS0 at begining of the boot process(MLO).
    I was worrying about reconfiguration of GPMC CS0 during boot process
    will cause access problem to CS0 if there are ongoing access to CS0.
    Because boot process is executing from XIP.

    So, after loading the code and pass execution to IRAM,
    it means loading is finished and there are no ongoing access to CS0.
    Am I right?

    best regards,
    g.f.

  • 0 in reply to g.f.
    TI__Guru**** 393215 points
    Yes, I think so.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 15510 points

    Sorry it took me so long to reply. The boot ROM does configure the NOR for 16MB as a default. Since NOR is XIP, there is no need for an MLO. As u-boot boots from NOR, it will copy itself to DDR and continue running from there. I believe gpmc_init is called when u-boot executes from DDR. That is where you can change GPMC_CONFIG7 to reflect your NOR is 64MB.

    Keep in mind that for non-multiplex NOR, the boot ROM only configures the first 12 bits of address space so that somewhere within the first 4k of address space, you have to do the rest of the pin-muxing. For multiplex NOR the boot ROM configures the first 16 bits of address space so that somewhere within the first 64k of address space you have to do the rest of the pin-muxing.

    The next release of the SDK for am335x will be 06.00.00.00, due out early July, and has support for multiplex NOR

    Steve K.

  • 0 in reply to Steve Kipisz
    Guru 15520 points

    Hi Biser and Steve,

    Thank you so much for answering my question.

    I understand by your help.

    So, do rest of the pinmuxing within 4k or 64k byte
    of address space(depend to which NOR boot mode are used).
    And GPMC register setting can be executed after u-boot are copied itself to DDR.

    Thank you.

    best regards,
    g.f.