SPI Edma completion interrupt

hi all

I use am3352 cpu. Now, Spi operate with edma3

I Want to be SPI TX Edma Completion Interrupt occurs.

However, 'Edma Complete Interrupt ' faster than 'Transfer complte' occurs.  

My configurations

1. MMU Enable, ICACHE and DACAHE Enable.

2.  paramSet.srcAddr = (unsigned int) buffer;

     paramSet.destAddr = (unsigned int) (MCSPI0_TX(1));

     paramSet.aCnt = 1;

     paramSet.bCnt = buffLength;

     paramSet.cCnt = 1;

     paramSet.srcBIdx = 1;     paramSet.destBIdx = 0;

      paramSet.srcCIdx = 0;     paramSet.destCIdx = 0;

      paramSet.linkAddr = (EDMA3CC_OPT(DUMMY_CH_NUM));     paramSet.bCntReload = 0;

     paramSet.opt = 0x00000000;

      paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);

      paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);   

      EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, &paramSet);

     TxDummyPaRAMConfEnable();

      EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);

3 . SPI SINGLE CHANNEL,  MASTER TX ONLY, 6MHZ, Setting

4.  Enable SPIDMA

5.  after tx complete, In Compete ISR , Wait IPR or IPRH Setting

6.  Clear Interrupt Flag, Disable SPI DMA

spi_clk                   _-_-_-_-_-_-_-_-_-_________

tx                            ___--___-___--_-_________  (TX Complete)

Interrupt complete -------------------_______--------  (GPIO Low Output in Edma Complete ISR)

                                                   14bytes           32bytes                                                                          

If SPI transfer 32bytes , Ideally, the interrupt must occur after the transfer 32bytes

However,  interrupt is generated after 14bytes  transfer.

After interrupt occurs , clock and the data is lost

What is the problem?

Thanks.