AM335x NAND prefetch engine: speed breakdown due to data cache writeback

Wolfgang Muees1

Genius 3685 points

Other Parts Discussed in Thread: MIO, AM3359

Hello *,

I am using the GPMC NAND flash interface with an 8bit NAND flash (cycle time == 40ns).

I am using the prefetch engine in read mode, doing polling to read the data from the FIFO.

If I try to read a page (2048 bytes) from NAND, I see the following behaviour:

- prefetch engine is started, first 100 bytes are transfered in full speed.

- after 100 bytes, prefetch engine is working in chunks of 4 bytes, chip select of NAND is inactive between accesses.

100 bytes is the best case, it gets worse if I disable the data cache.

So I came to the conclusion that the flush of the data cache (to DDR3 RAM) is interrupting the prefetch engine.

I tried to use the internal RAM at 0x402F0400 as data buffer, but this is also interrupting the prefetch engine.

I have NOT tried to use DMA, but I expect no better behaviour as DMA has to write to DDR3 ram also.

So, what is the recommended procedure to programm the prefetch engine to get the expected performance?

TI must somehow have validated the prefetch performance in the release process?

best regards

Wolfgang

over 12 years ago

0 Wolfgang Muees1 over 12 years ago

Genius 3685 points

OK,

I found the source of the problem.... it was not the data cache, but the slow access time of the GPMC.

The interface between MPU and GPMC is capable of about 3 Mio. accesses per second. So, if you read 32bit at once, you will only get 12 MByte/sec from the NAND prefetch engine.

I had not expected this CPU beeing so slow...

0 John Murphy1 over 12 years ago in reply to Wolfgang Muees1

Expert 1210 points

I was pretty amazed at how slow the uboot and Linux NAND drivers are: a few MByte/sec. I don't think they even enable prefetch or DMA. uboot can be sped up slightly by enabling d-cache.

Are you working on uboot or Linux or other?

0 Wolfgang Muees1 over 12 years ago in reply to John Murphy1

Genius 3685 points

John,

I am working on uboot AND Linux. I have enabled D-Cache and I-Cache in uboot, and have a tuned prefetch/poll implementation. This gives me a raw transfer speed of 12MBytes/s for reading, and 16 MBytes/s for writing. More is only possible with DMA, because the bottleneck is the interface between MPU and GPMC. I have enabled/fixed the nand device busy flag handling in both uboot and linux.

0 John Murphy1 over 12 years ago in reply to Wolfgang Muees1

Expert 1210 points

Wow, that's a big improvement. Please can you share the patches. :-)

I can test them on 8-bit and 16-bit NAND (i.e. MT29F4G08ABADAWP / MT29F4G16ABADAWP devices), and they would certainly help with boot up time.

0 Michael Gabler over 12 years ago in reply to Wolfgang Muees1

Prodigy 30 points

It would be really great if you could share your sources (U-Boot).

We currently write a NAND driver for proprietary OS, and we stuck at 3,3 MB/s for raw reading, which is far below your values. We also use U-Boot version 2013.01 (from TI) , which has raw read speed < 1 MB/s, which is awfull.

It would really help if we could see how you have done that NAND GPMC stuff.

0 John Murphy1 over 12 years ago in reply to Michael Gabler

Expert 1210 points

I think T.I. needs to put some more effort into fixing this. The NAND read performance is really poor in both u-boot and the Linux kernel. Not everyone uses SD cards!

0 Wolfgang Muees1 over 12 years ago in reply to John Murphy1

Genius 3685 points

I have attached a patch file with all modifications we have done to u-boot.

The nand flash is a standard 2048Byte Page 8 bit type, and there might be some problems left for 16bit flashes.

The nand flash is driven with a cycle time of 40ns, which is sufficient for all common nand flashes.

Subpage writes are disabled (missing software to detect subpage write ECC replacement).

The ECC is hardware ECC (same as used in boot rom, 13bytes ECC + 1 byte 0x00).

U-boot was downloaded from TI repository, last checkin was:

> e5521fb3eebfb062073d0e3dd02f70b4c8994aec

> Vishveshwar Bhat <vishveshwar.bhat@ti.com> 2013-03-26 13:39:39

> FASTBOOT: Fix on AM335x

Limiting speed factor for NAND is missing DMA engine, to overcome the GPMC bottleneck.

maybe this code will help you...

regards

Wolfgang

uboot_diff.patch.tar.gz

0 John Murphy1 over 12 years ago in reply to Wolfgang Muees1

Expert 1210 points

Thanks, looks good!

0 Michael Gabler over 12 years ago in reply to Wolfgang Muees1

Prodigy 30 points

Thanks, Wolfgang. We will try to adapt the settings of your patch to U-Boot and our own software.

Regarding read performance, you talked about 12 MB/s RAW. What do you mean with RAW? Does it include ECC BCH8 Hardware calculation?

We currently have a running software including prefetch engine, but we only achieve a maximum read transfer (incl. ECC) of ~3.5 MB/s. This seems to be comparable with the performance the TI guys are mentioning in their PSP guide (http://processors.wiki.ti.com/index.php/AM335x-PSP_04.06.00.08_Features_and_Performance_Guide). Hence I am still wondering about the 12MB/s....

0 Wolfgang Muees1 over 12 years ago in reply to Michael Gabler

Genius 3685 points

Michael,

RAW == transfer speed at the GPMC interface to the (8 bit) NAND chip, checked with an oscilloscope.

For your implementation, check for

a) a working Ready/Busy flag check

b) an optimal timing of the GPMC interface. This should give you a max. transfer speed of 25 MByte/s.

c) Instruction and data cache active.

regards

Wolfgang

0 John Murphy1 over 12 years ago in reply to Wolfgang Muees1

Expert 1210 points

Hi Wolfgang,

Thanks for the u-boot patches, they are very helpful.

I guess the NAND prefetch idea is also useful in the Linux NAND driver. Did you write patches for prefetch and poll improvements for Linux? It would be most appreciated if you could post the patches (or source files) that you modified in Linux.

Cheers,

John.

0 John Murphy1 over 12 years ago in reply to John Murphy1

Expert 1210 points

Thanks, the u-boot patches worked well.

We had to do "dcache on" right before doing the nand read, this helps as the dcache is disabled in the latest TI SDK 6 u-boot. And dcache also helps speed up the uncompressing of Linux.

We got about 3.3 MB/sec (16-bit NAND) in uboot:

[3.930623 0.000108] NAND read: device 0 offset 0x280000, size 0x500000
[5.539086 1.608463] 5242880 bytes read: OK
[5.541282 0.002196] ## Booting kernel from Legacy Image at 80200000 ...
[5.546825 0.005543] Image Name: Linux-3.2.0
[5.549816 0.002991] Image Type: ARM Linux Kernel Image (uncompressed)
[5.556683 0.006867] Data Size: 4885912 Bytes = 4.7 MiB
[5.561492 0.004809] Load Address: 80008000
[5.563560 0.002068] Entry Point: 80008000
[5.565207 0.001647] Verifying Checksum ... OK
[5.729327 0.164120] Loading Kernel Image ... OK
[5.730395 0.001068] OK
[5.730513 0.000118]
[5.730550 0.000037] Starting kernel ...
[5.730998 0.000448]
[5.731035 0.000037] Uncompressing Linux... done, booting the kernel.
[6.811528 1.080493] [ 0.000000] Linux version 3.2.0 (johnmu@swvmu01-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #2 Fri Nov 15 13:46:10 NZDT 2013
[6.830587 0.019059] [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[6.837578 0.006991] [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[6.845672 0.008094] [ 0.000000] Machine: am335xevm

0 Wolfgang Muees1 over 12 years ago in reply to John Murphy1

Genius 3685 points

John,

3,3MB/s for a 16 bit NAND is close to nothing.

I suspect that your flash timing values and/or the ready/busy logic is wrong.

I use dcache and icache in u-boot. It's working fine here.

regards

Wolfgang

0 John Murphy1 over 12 years ago in reply to Wolfgang Muees1

Expert 1210 points

Thanks.

I'm not sure what to try next. I don't think it is the NAND device timings. I checked the speed before and after using your greatly improved timing parameters (M_NAND_GPMC_CONFIG*), and so I know they are active, but they didn't make a huge improvement.

I tested 8-bit and 16-bit NAND devices, and there wasn't much speed difference there either, so I don't think the speed bottleneck is on the external GPMC to NAND interface (as you suggest).

I've enabled dcache using the "dcache on" u-boot command, and that helped significantly. icache is on by default.

I've patched in your prefetech code "nand->read_buf = read_buf_pref", and enabled the default omap device ready "nand->dev_ready = omap_dev_ready", which checks "int omap_dev_ready(struct mtd_info *mtd) { return gpmc_cfg->status & (1 << 8); }".

And the mux.c enables the GPMC_WAIT0: "{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */".

So I'm not sure what else to try... Roughly what kind of speed do you get for the 8-bit u-boot "nand read xxxx" command?

Perhaps the issue is not in the NAND read, but some other area. I'm using BCH-8 HW ECC, is that what you used as well?

0 Dav01 over 12 years ago in reply to John Murphy1

Expert 2300 points

Checking in on this old thread. Is this NAND performance patched and pushed in the main-line repository now?

best David

0 Gary Wu over 11 years ago in reply to John Murphy1

TI__Expert 3313 points

Hi John,

Could you guide me how to get the patch work?

It always says "patch: **** malformed patch at line 844: ".

And I tried to modify the directory of auer_am335x to am335x. But it still doesn't work.

BTW, I am using the u-boot from below link.

https://gitorious.org/rowboat/u-boot/commits/8d3ec2d81a70368f2df04164537ab4ca22e6d94e

0 John Murphy1 over 11 years ago in reply to Gary Wu

Expert 1210 points

The original path is from Wolfgang. I've also enabled the "dcache" when doing the nand read.

I applied it manually to my build of u-boot (based on ti-sdk-06.00.00). You will need to apply it by hand if it doesn't work, but it should be easy if you use the ti-sdk-06.00.00 u-boot:

Fullscreen 2043.nand.txt Download

Index: u-boot/arch/arm/include/asm/arch-am33xx/mem.h
===================================================================
--- u-boot/arch/arm/include/asm/arch-am33xx/mem.h	(revision 3348)
+++ u-boot/arch/arm/include/asm/arch-am33xx/mem.h	(revision 3349)
@@ -29,7 +29,7 @@
 
 #ifndef _MEM_H_
 #define _MEM_H_
-
+#include "asm/arch-omap3/omap3-regs.h"
 /*
  * GPMC settings -
  * Definitions is as per the following format
@@ -53,6 +53,58 @@
 #define GPMC_SIZE_32M		0xE
 #define GPMC_SIZE_16M		0xF
 
+
+/* Note: GPMC Clock = Core Clock M4 / 2 == 100 MHz, d.h. alles in n*10ns */
+/* Note: RDcycle und WrCycle >= 4 bei Verwendung der BCH ECC (Kap. 7.1.3.3.12.3.2.1)
+ *                 U-Boot          Linux */                    
+#define _CSROFF     4         /* 44ns */    
+#define _CSWOFF     4         /* 44ns */
+#define _ADON       0         /* 6ns */
+#define _ADROFF     4         /* 34ns */
+#define _ADWOFF     4         /* 44ns */
+#define _OEON       1         /* 0ns */
+#define _OEOFF      3         /* 54ns */
+#define _WEON       1         /* 0ns */
+#define _WEOFF      3         /* 40ns */
+#define _RDCY       4         /* 82ns */
+#define _WRCY       4         /* 82ns */
+#define _RDACC      4         /* 64ns */
+#define _CSHIGH     6         /* 0ns */     /* 100ns tADL! 60ns tWHR! */
+#define _WBURST     0         /* 0ns */
+#define _WRACC      4         /* 40ns */
+#define _BTURN      9         /* ??? */     /* 100ns tRHW */
+
+/* Info zur Prefetch-Engine:
+ * =========================
+ *  GPMC_PREFETCH_CONFIG1[27] ENABLEOPTIMIZEDACCESS = 1 (to remove _CSHIGH)
+ *  GPMC_PREFETCH_CONFIG1[30-28] CYCLEOPTIMIZATION  = 0 (Zugriff kann nicht weiter verkuerzt werden)
+ */
+
+/* CONFIG1: Type of Device, Type of Access */
+
+#ifdef CONFIG_POLARIS_PREFETCH
+#define M_NAND_GPMC_CONFIG1 ( GPMCFCLKDIVIDER(0) | 0 /* TIMEPARAGRANULARITY */ | 0 /* MUXADDDATA */ | \
+    DEVICETYPE_NAND | DEVICESIZE_16BIT | WAITPINSELECT(0) | WAITMONITORINGTIME(0) | \
+	0 /* WAITWRITEMONITORING */ | 0 /* WAITREADMONITORING */ | ATTACHEDDEVICEPAGELENGTH(0) | \
+	CLKACTIVATIONTIME(0) | 0 /* WRITETYPE */ | 0 /* WRITEMULTIPLE */ | 0 /* READTYPE */ | \
+	0 /* READMULTIPLE */ | 0 /* WRAPBURST */ )
+/* CONFIG2: Chip Select */        
+#define M_NAND_GPMC_CONFIG2 (CSWROFFTIME(_CSWOFF) | CSRDOFFTIME(_CSROFF) | CSONTIME(0) | 0 /* CSEXTRADELAY */ )
+/* CONFIG3: ADV/ALE */
+#define M_NAND_GPMC_CONFIG3 ( ADVWROFFTIME(_ADWOFF) | ADVRDOFFTIME(_ADROFF) | 0 /* ADVEXTRADELAY */ | ADVONTIME(_ADON) )
+/* CONFIG4: WE/OE */
+#define M_NAND_GPMC_CONFIG4 ( WEOFFTIME(_WEOFF) | 0 /* WEEXTRADELAY */ | WEONTIME(_WEON) | \
+	OEOFFTIME(_OEOFF) | 0 /* OEEXTRADELAY */ | OEONTIME(_OEON) )
+/* CONFIG5: Cycle Timing */
+#define M_NAND_GPMC_CONFIG5 ( PAGEBURSTACCESSTIME(0) | RDACCESSTIME(_RDACC) | WRCYCLETIME(_WRCY) | RDCYCLETIME(_RDCY) )
+/* CONFIG6: Rest of the Pack */
+#define M_NAND_GPMC_CONFIG6 ( WRACCESSTIME(_WRACC) | WRDATAONADMUXBUS(_WBURST) | CYCLE2CYCLEDELAY(_CSHIGH) | \
+	CYCLE2CYCLESAMECSEN | 0 /* CYCLE2CYCLEDIFFCSEN */ | BUSTURNAROUND(_BTURN) )
+/* CONFIG7: Address Mapping */
+#define M_NAND_GPMC_CONFIG7	MASKADDRESS(0x00) | CSVALID | BASEADDRESS(0x0)
+
+#else
+
 #ifdef CONFIG_POLARIS_NAND_16
 /* jfm 16-bit and half-speed for 16-bit S2 and 16-bit EVM */
 /* #define M_NAND_GPMC_CONFIG1	0x00001810 */
@@ -70,6 +122,8 @@
 #define M_NAND_GPMC_CONFIG6	0x16000f80
 #define M_NAND_GPMC_CONFIG7	0x00000008
 
+#endif
+
 /* NOR chip on NOR module for Beaglebone */
 #define STNOR_GPMC_CONFIG1	0x00001200
 #define STNOR_GPMC_CONFIG2	0x00101000
Index: u-boot/arch/arm/include/asm/arch-am33xx/cpu.h
===================================================================
--- u-boot/arch/arm/include/asm/arch-am33xx/cpu.h	(revision 3348)
+++ u-boot/arch/arm/include/asm/arch-am33xx/cpu.h	(revision 3349)
@@ -96,7 +96,11 @@
 	u32 status;		/* 0x54 */
 	u8 res5[0x8];		/* 0x58 */
 	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
+    u32 pref_config1;       /* 0x1E0 */
+    u32 pref_config2;       /* 0x1E4 */
+    u8 res6[0x4];           /* 0x1E8 */
+    u32 pref_control;       /* 0x1EC */
+    u32 pref_status;        /* 0x1F0 */
 	u32 ecc_config;		/* 0x1F4 */
 	u32 ecc_control;	/* 0x1F8 */
 	u32 ecc_size_config;	/* 0x1FC */
Index: u-boot/arch/arm/cpu/armv7/am33xx/mem.c
===================================================================
--- u-boot/arch/arm/cpu/armv7/am33xx/mem.c	(revision 3348)
+++ u-boot/arch/arm/cpu/armv7/am33xx/mem.c	(revision 3349)
@@ -42,7 +42,8 @@
 	M_NAND_GPMC_CONFIG3,
 	M_NAND_GPMC_CONFIG4,
 	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6, 0
+	M_NAND_GPMC_CONFIG6, 
+	M_NAND_GPMC_CONFIG7, 
 };
 #endif
 
@@ -72,9 +73,7 @@
 	writel(gpmc_config[3], &cs->config4);
 	writel(gpmc_config[4], &cs->config5);
 	writel(gpmc_config[5], &cs->config6);
-	/* Enable the config */
-	writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
-		(1 << 6)), &cs->config7);
+        writel(gpmc_config[6] | CSVALID, &cs->config7);
 	sdelay(2000);
 }
 
@@ -113,8 +112,8 @@
 #ifdef CONFIG_CMD_NAND
 	gpmc_config = gpmc_m_nand;
 
-	base = PISMO1_NAND_BASE;
-	size = PISMO1_NAND_SIZE;
+    base = 0; // PISMO1_NAND_BASE;
+    size = 0; //PISMO1_NAND_SIZE;
 	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 #endif
 
Index: u-boot/boards.cfg
===================================================================
--- u-boot/boards.cfg	(revision 3348)
+++ u-boot/boards.cfg	(revision 3349)
@@ -230,10 +230,10 @@
 integratorap_cm946es         arm         arm946es    integrator          armltd         -               integratorap:CM946ES
 integratorcp_cm946es         arm         arm946es    integrator          armltd         -               integratorcp:CM946ES
 ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
-am335x_evm                   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS
-am335x_evm_nand16            arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_NAND_16
-am335x_evm_prodtest          arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_PRODTEST
-am335x_evm_prodtest_nand16   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_PRODTEST,POLARIS_NAND_16
+am335x_evm                   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_PREFETCH
+am335x_evm_nand16            arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_NAND_16,POLARIS_PREFETCH
+am335x_evm_prodtest          arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_PRODTEST,POLARIS_PREFETCH
+am335x_evm_prodtest_nand16   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,POLARIS,POLARIS_PRODTEST,POLARIS_NAND_16,POLARIS_PREFETCH
 am335x_evm_nor               arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NOR
 am335x_evm_norboot           arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT
 am335x_evm_spiboot           arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT
Index: u-boot/drivers/mtd/nand/nand_spl_simple.c
===================================================================
--- u-boot/drivers/mtd/nand/nand_spl_simple.c	(revision 3348)
+++ u-boot/drivers/mtd/nand/nand_spl_simple.c	(revision 3349)
@@ -59,14 +59,24 @@
 		       NAND_CTRL_ALE); /* A[28:25] */
 #endif
 	/* Latch in address */
-	this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+    this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+    if (cmd == NAND_CMD_RNDOUT) {
+        /* no wait necessary */
+        return 0;
+    }
 
 	/*
 	 * Wait a while for the data to be ready
 	 */
-	while (!this->dev_ready(&mtd))
-		;
+    ndelay(100);
+    if (!this->dev_ready) {
+        udelay(this->chip_delay);
+        return;
+    }
 
+    while(!this->dev_ready(&mtd))
+            ;
+
 	return 0;
 }
 #else
Index: u-boot/drivers/mtd/nand/omap_gpmc.c
===================================================================
--- u-boot/drivers/mtd/nand/omap_gpmc.c	(revision 3348)
+++ u-boot/drivers/mtd/nand/omap_gpmc.c	(revision 3349)
@@ -266,6 +266,168 @@
 	.nibbles = ECC_BCH8_NIBBLES
 };
 
+#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
+#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
+
+#define PREFETCH_ENABLEOPTIMIZEDACCESS	 (0x1 << 27)
+
+#define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      (((val) >> 24) & 0x7F)
+#define GPMC_PREFETCH_STATUS_COUNT(val) ((val) & 0x00003fff)
+
+#define CS_NUM_SHIFT            24
+#define ENABLE_PREFETCH         (0x1 << 7)
+//#define DMA_MPU_MODE            2
+//#define OMAP_NAND_TIMEOUT_MS    5000
+
+//#define PRINT_REG(x)
+#define PRINT_REG(x) printf("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
+
+#define barrier() __asm__ __volatile__("": : :"memory")
+
+#define FIFO_IOADDR 0x100000  // Prefetch IO addr
+
+
+/**
+ * gpmc_prefetch_enable - configures and starts prefetch transfer
+ * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @u32_count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ */
+static inline void gpmc_prefetch_enable(int cs, int fifo_th, unsigned int u32_count, int is_write)
+{
+        writel(u32_count, &gpmc_cfg->pref_config2);
+
+        /* Set the prefetch read / post write and enable the engine.
+         * Set which cs is has requested for.
+         */
+        uint32_t val = (cs << CS_NUM_SHIFT) |
+            PREFETCH_ENABLEOPTIMIZEDACCESS |
+            PREFETCH_FIFOTHRESHOLD(fifo_th) |
+            ENABLE_PREFETCH |
+            (0x1 & is_write);
+        writel(val, &gpmc_cfg->pref_config1);
+
+                /*  Start the prefetch engine */
+        writel(0x1, &gpmc_cfg->pref_control);
+}
+
+
+/**
+ * gpmc_prefetch_reset - disables and stops the prefetch engine
+ */
+static inline void gpmc_prefetch_reset(void)
+{
+        /* Stop the PFPW engine */
+    writel(0x0, &gpmc_cfg->pref_control);
+
+        /* Reset/disable the PFPW engine */
+    writel(0x0, &gpmc_cfg->pref_config1);
+}
+
+
+/**
+ * read_buf_pref - read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
+{
+    // Note: FIFOTHRESHOLDSTATUS is not working for MAX=40H
+    // Note: FIFO threshold not needed here
+    gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX / 2, len, 0);
+
+    do {
+        // Get number of bytes waiting in the FIFO
+        uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
+        // Alignment of Destination Buffer
+        while (read_bytes && ((unsigned int)buf & 3)) {
+			
+            *buf++ = readb(FIFO_IOADDR);
+            read_bytes--;
+            len--;
+        }
+        // Use maximum word size (32bit) inside this loop, because speed is limited by
+        // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
+        len -= read_bytes & ~3;
+        while (read_bytes >= 4) {
+            *((uint32_t*)buf) = readl(FIFO_IOADDR);
+            buf += 4;
+            read_bytes -= 4;
+        }
+        // Transfer the last (non-aligned) bytes only at the last iteration,
+        // to maintain full speed up to the end of the transfer.
+        if (read_bytes == len) {
+            while (read_bytes) {
+                *buf++ = readb(FIFO_IOADDR);
+                read_bytes--;
+            }
+            len = 0;
+        }
+    } while (len > 0);
+    gpmc_prefetch_reset();
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+/**
+ * write_buf_pref - write buffer to NAND controller
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
+{
+    /*  configure and start prefetch transfer */
+    gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX / 2, len, 1);
+
+    while (len) {
+        // Get number of free bytes in the FIFO
+        uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
+
+        // don't write more bytes than requested
+        if (write_bytes > len)
+            write_bytes = len;
+
+        // Alignment of Source Buffer
+        while (write_bytes && ((unsigned int)buf & 3)) {
+            writeb(*buf++, FIFO_IOADDR);
+            write_bytes--;
+            len--;
+        }
+
+        // Use maximum word size (32bit) inside this loop, because speed is limited by
+        // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
+        len -= write_bytes & ~3;
+        while (write_bytes >= 4) {
+            writel(*((uint32_t*)buf), FIFO_IOADDR);
+            buf += 4;
+            write_bytes -= 4;
+        }
+
+        // Transfer the last (non-aligned) bytes only at the last iteration,
+        // to maintain full speed up to the end of the transfer.
+        if (write_bytes == len) {
+            while (write_bytes) {
+                writeb(*buf++, FIFO_IOADDR);
+                write_bytes--;
+            }
+            len = 0;
+        }
+    }
+
+    /* wait for data to flushed-out before reset the prefetch */
+    while (GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status))) {
+        cpu_relax();
+    }
+
+   /* disable and stop the PFPW engine */
+   gpmc_prefetch_reset();
+}
+#endif
+
+
 /*
  * omap_read_bch8_result - Read BCH result for BCH8 level
  *
@@ -765,13 +927,15 @@
 #endif
 #endif
 
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_POLARIS_PREFETCH
 	if (nand->options & NAND_BUSWIDTH_16)
-		nand->read_buf = nand_read_buf16;
+        nand->read_buf = read_buf_pref;
 	else
-		nand->read_buf = nand_read_buf;
-	nand->dev_ready = omap_spl_dev_ready;
+        nand->read_buf = read_buf_pref;
 #endif
+#ifdef CONFIG_SPL_BUILD
+    nand->dev_ready = omap_spl_dev_ready;
+#endif
 
 	return 0;
 }

0 Gary Wu over 11 years ago in reply to John Murphy1

TI__Expert 3313 points

Thanks, John.

I see a group of GPMC timing for nand configuration in mem.h.

It's for the NAND in GPEVM? What's your version of GPEVM?

0 Gary Wu over 11 years ago in reply to Gary Wu

TI__Expert 3313 points

My GPVEM is Rev 1.1A with AM3359 720M and 8 bit NAND flash.

After adding your patch and modified DEVICESIZE_16BIT to DEVICESIZE_8BIT, it doesn't work.

There seems be some ECC errors.

The log:

U-Boot SPL 2013.01.01 (Jun 24 2014 - 15:36:24)
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Host mode controller at 47401800 using PIO, IRQ 0
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.

BTW, is your patch based on orginal TI-sdk-06.00 uboot?

From the patch, I didn't see any changes for ECC.

0 John Murphy1 over 11 years ago in reply to Gary Wu

Expert 1210 points

Yes, it was based on ti-sdk-06.00 u-boot.

If it is timing related, you could try increasing the timings or use TIMEPARAGRANULARITY in NAND_GPMC_CONFIG1 to double the timings.

But it is probably a mismatch between the ECC scheme you used to program the flash and to read it.

During debugging / development, it is often easier to build and run the SD card build of u-boot, and boot off the SD card. Then at the u-boot prompt you can use the various u-boot "nand" commands to try and read/write the NAND.

0 Gary Wu over 11 years ago in reply to John Murphy1

TI__Expert 3313 points

Thanks for your suggestion.

I agreed with you and tried to boot from SD. But it failed.

The log is

U-Boot SPL 2013.01.01 (Jun 24 2014 - 13:24:48)
### ERROR ### Please RESET the board ###

Meanwhile, it works when programming by nand-flash-writer before adding your patch. And I didn't see any changes about ECC in the patch. So confusing.

0 Gary Wu over 11 years ago in reply to Gary Wu

TI__Expert 3313 points

There may be something wrong in my GPEVM.

After changing a new GPEVM, it made it to boot from SD card.

But there is still ECC error.

I could write images into NAND flash with u-boot commands. But it reported "ECC: uncorrectable" when I read NAND flash at once.

U-Boot# nand erase.chip

NAND erase.chip: device 0 whole chip
Erasing at 0xffe0000 -- 100% complete.
OK
U-Boot# nand read 0x82000000 0x0 0x20000

NAND read: device 0 offset 0x0, size 0x20000
131072 bytes read: OK
U-Boot# mmc rescan
U-Boot# mw.b 0x82000000 0xFF 0x20000
U-Boot# fatload mmc 0 0x82000000 MLO
reading MLO
44327 bytes read in 6 ms (7 MiB/s)

U-Boot# nand erase 0x0 0x20000

NAND erase: device 0 offset 0x0, size 0x20000
Erasing at 0x0 -- 100% complete.
OK
U-Boot# nand write.i 0x82000000 0x0 0x20000

NAND write: device 0 offset 0x0, size 0x20000
131072 bytes written: OK
U-Boot# nand read 0x82000000 0x0 0x20000

NAND read: device 0 offset 0x0, size 0x20000
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.
ECC: uncorrectable.

.............

NAND read from offset 0 failed -74
0 bytes read: ERROR

0 John Murphy1 over 11 years ago in reply to Gary Wu

Expert 1210 points

OK. You can try nand.dump and see if that show anything strange.

e.g.

U-Boot# nand dump.oob 0
Page 00000000 dump:
OOB:
ff ff c8 b0 e8 12 b2 4a
63 70 83 0f c6 76 57 00
a8 d9 8d 1a 4e 09 2f e9
b9 49 fe bb 74 00 89 1c
4f 4a 8b 60 76 a8 e2 bb
71 1f 1d 00 a3 2a 71 9f
0e 98 88 3b 0f 9c 73 e3
58 00 ff ff ff ff ff ff
U-Boot# nand dump 0
Page 00000000 dump:
40 00 00 00 0c 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 43 48 53 45 54 54 49 4e 47 53 00 00
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c1 c0 c0 c0 00 01 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
fb 7a 01 00 00 04 2f 40 14 00 00 ea 14 f0 9f e5
14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5
14 f0 9f e5 14 f0 9f e5 20 04 2f 40 24 04 2f 40
28 04 2f 40 2c 04 2f 40 30 04 2f 40 34 04 2f 40
38 04 2f 40 78 56 34 12 00 00 80 80 00 fc d0 3f
d4 23 01 00 90 04 d1 3f d4 23 01 00 de c0 ad 0b
3e 03 00 eb 00 00 0f e1 1f 00 c0 e3 d3 00 80 e3
00 f0 29 e1 10 0f 11 ee 02 0a c0 e3 10 0f 01 ee
68 00 9f e5 10 0f 0c ee 09 00 00 eb 16 00 00 eb
9c 03 00 eb 15 0f 07 ee 9a 0f 07 ee 95 0f 07 ee
48 00 9f e5 09 00 80 e0 10 0f 0c ee 1e ff 2f e1
1e ff 2f e1 00 00 a0 e3 17 0f 08 ee 15 0f 07 ee
d5 0f 07 ee 9a 0f 07 ee 95 0f 07 ee 10 0f 11 ee
02 0a c0 e3 07 00 c0 e3 02 00 80 e3 02 0b 80 e3
01 0a 80 e3 10 0f 01 ee 0e f0 a0 e1 12 03 00 ea
00 04 2f 40 00 f0 20 e3 38 40 2d e9 00 40 a0 e1
04 10 a0 e1 84 00 9f e5 1a 09 00 eb 80 30 9f e5
00 20 93 e5 88 10 92 e5 00 20 93 e5 2c c0 92 e5
00 20 93 e5 a8 00 92 e5 00 20 93 e5 04 50 a0 e3
88 50 82 e5 00 50 93 e5 54 20 9f e5 20 50 95 e5
01 0c 55 e3 fa ff ff 1a ac 39 a0 e1 83 39 a0 e1
17 30 83 e3 04 44 83 e1 00 c0 92 e5 1f 00 c0 e3
01 00 80 e3 2c 40 8c e5 00 30 92 e5 07 10 81 e3
a8 00 83 e5 00 30 92 e5 88 10 83 e5 00 30 92 e5
20 30 93 e5 01 00 53 e3 fb ff ff 1a 38 80 bd e8
0a f7 2f 40 60 28 30 40 f8 40 2d e9 00 40 a0 e1
04 10 a0 e1 20 01 9f e5 f2 08 00 eb 1c 31 9f e5
00 20 93 e5 90 20 92 e5 00 10 93 e5 68 50 91 e5
00 10 93 e5 80 c0 91 e5 00 10 93 e5 84 00 91 e5
00 10 93 e5 d8 10 91 e5 00 60 93 e5 04 70 a0 e3
90 70 86 e5 03 70 a0 e1 00 60 97 e5 dc 30 9f e5
5c 60 96 e5 01 0c 56 e3 fa ff ff 1a 32 00 54 e3
a5 49 a0 e1 84 49 a0 e1 17 00 00 1a 32 4c 84 e3
17 40 84 e3 00 50 93 e5 1f c0 cc e3 01 c0 8c e3
68 40 85 e5 00 40 93 e5 1f 00 c0 e3 01 00 80 e3
80 c0 84 e5 00 c0 93 e5 1f 10 c1 e3 01 10 81 e3
84 00 8c e5 00 00 93 e5 07 20 82 e3 d8 10 80 e5
00 10 93 e5 90 20 81 e5 00 20 93 e5 5c 20 92 e5
01 00 52 e3 fb ff ff 1a f8 80 bd e8 fa 4b 84 e3
17 40 84 e3 00 50 93 e5 1f c0 cc e3 0a c0 8c e3
68 40 85 e5 00 40 93 e5 1f 00 c0 e3 08 00 80 e3
80 c0 84 e5 00 c0 93 e5 1f 10 c1 e3 04 10 81 e3
84 00 8c e5 00 00 93 e5 07 20 82 e3 d8 10 80 e5
00 10 93 e5 90 20 81 e5 00 20 93 e5 5c 20 92 e5
01 00 52 e3 fb ff ff 1a f8 80 bd e8 27 f7 2f 40
60 28 30 40 84 30 9f e5 30 40 2d e9 00 20 93 e5
94 10 92 e5 00 20 93 e5 40 40 92 e5 00 20 93 e5
a0 c0 92 e5 07 10 c1 e3 04 50 81 e3 00 20 93 e5
94 50 82 e5 00 50 93 e5 50 20 9f e5 34 50 95 e5
01 0c 15 e3 fa ff ff 0a a4 39 a0 e1 83 39 a0 e1
17 30 83 e3 00 34 83 e1 00 40 92 e5 1f 00 cc e3
01 00 80 e3 40 30 84 e5 00 30 92 e5 07 10 81 e3
a0 00 83 e5 00 30 92 e5 94 10 83 e5 00 30 92 e5
34 30 93 e5 01 00 13 e3 fb ff ff 0a 30 80 bd e8
60 28 30 40 24 30 9f e5 02 20 a0 e3 00 10 93 e5
d0 20 81 e5 00 10 93 e5 28 20 81 e5 00 20 93 e5
28 20 92 e5 02 00 52 e3 fb ff ff 1a 1e ff 2f e1
64 28 30 40 10 40 2d e9 4b 0f a0 e3 55 ff ff eb
32 00 a0 e3 7b ff ff eb 5c 33 9f e5 00 20 93 e5
8c 10 92 e5 00 20 93 e5 9c c0 92 e5 00 20 93 e5
ac 00 92 e5 00 20 93 e5 04 40 a0 e3 8c 40 82 e5
00 40 93 e5 30 23 9f e5 70 40 94 e5 01 0c 54 e3
fa ff ff 1a ac 39 a0 e1 83 39 a0 e1 0f 39 83 e3
17 30 83 e3 00 c0 92 e5 7f 00 c0 e3 05 00 80 e3
9c 30 8c e5 00 30 92 e5 07 10 81 e3 ac 00 83 e5
00 30 92 e5 8c 10 83 e5 00 30 92 e5 70 30 93 e5
01 00 53 e3 fb ff ff 1a dc 32 9f e5 03 2c a0 e3
00 30 93 e5 7c 20 83 e5 d0 32 9f e5 02 10 a0 e3
00 20 93 e5 e0 10 82 e5 03 10 a0 e1 00 20 91 e5
b8 32 9f e5 e0 20 92 e5 02 00 52 e3 fa ff ff 1a
00 10 93 e5 60 20 81 e5 03 10 a0 e1 00 20 91 e5
60 20 92 e5 02 00 52 e3 90 32 9f e5 fa ff ff 1a
00 10 93 e5 64 20 81 e5 00 20 93 e5 64 20 92 e5
02 00 52 e3 fb ff ff 1a 6c 32 9f e5 00 10 93 e5
0c 20 81 e5 00 20 93 e5 0c 20 92 e5 02 00 52 e3
fb ff ff 1a 54 32 9f e5 00 10 93 e5 dc 20 81 e5
03 10 a0 e1 00 20 91 e5 40 32 9f e5 dc 20 92 e5
02 00 52 e3 fa ff ff 1a 00 10 93 e5 20 21 81 e5
00 20 93 e5 20 21 92 e5 02 00 52 e3 fb ff ff 1a
14 32 9f e5 00 10 93 e5 03 00 a0 e1 08 20 81 e5
00 20 90 e5 00 12 9f e5 08 30 92 e5 02 00 53 e3
fa ff ff 1a f4 21 9f e5 00 00 92 e5 0c 30 80 e5
00 00 92 e5 00 30 80 e5 00 00 91 e5 00 30 80 e5
00 00 92 e5 08 30 80 e5 00 00 92 e5 04 30 80 e5
00 00 91 e5 04 30 80 e5 00 30 91 e5 04 30 93 e5
02 00 53 e3 fb ff ff 1a b0 11 9f e5 00 20 92 e5
80 30 82 e5 00 30 91 e5 80 20 93 e5 02 00 52 e3
fb ff ff 1a 98 31 9f e5 01 10 a0 e3 00 30 93 e5
08 10 83 e5 80 31 9f e5 00 10 93 e5 b4 20 81 e5
00 20 93 e5 b4 20 92 e5 02 00 52 e3 fb ff ff 1a
68 31 9f e5 00 10 93 e5 30 20 81 e5 03 10 a0 e1
00 20 91 e5 54 31 9f e5 30 20 92 e5 02 00 52 e3
fa ff ff 1a 00 10 93 e5 40 20 81 e5 03 10 a0 e1
00 20 91 e5 40 20 92 e5 02 00 52 e3 2c 31 9f e5
fa ff ff 1a 00 10 93 e5 3c 20 81 e5 00 20 93 e5
3c 20 92 e5 02 00 52 e3 fb ff ff 1a 08 31 9f e5
OOB:
ff ff c8 b0 e8 12 b2 4a
63 70 83 0f c6 76 57 00
a8 d9 8d 1a 4e 09 2f e9
b9 49 fe bb 74 00 89 1c
4f 4a 8b 60 76 a8 e2 bb
71 1f 1d 00 a3 2a 71 9f
0e 98 88 3b 0f 9c 73 e3
58 00 ff ff ff ff ff ff
U-Boot#

0 Gary Wu over 11 years ago in reply to John Murphy1

TI__Expert 3313 points

orignal uboot with your patch.

Below is my log :

U-Boot# nand dump.oob 0
Page 00000000 dump:
OOB:
ff ff c8 b0 e8 12 b2 4a
63 70 83 0f c6 76 57 00
97 44 d0 70 e4 83 88 03
de d2 0b ae bc 00 12 39
d2 12 c2 02 57 a1 69 b0
81 29 45 00 5a 42 b2 08
68 5e c1 f0 18 98 cb 5a
9a 00 ff ff ff ff ff ff
U-Boot# nand dump 0
Page 00000000 dump:
40 00 00 00 0c 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 43 48 53 41 54 54 41 4e 47 53 00 00
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c1 c0 c0 c0 00 01 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
3d 87 01 00 00 04 2f 40 14 00 00 ea 10 f0 9f e5
14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5
14 f0 9f e5 14 f0 9f e5 20 04 2f 40 24 04 2f 40
28 00 2f 40 2c 04 2f 40 30 04 2f 40 34 04 2f 40
38 00 2f 40 78 52 34 12 00 00 80 80 00 fc d0 3f
50 79 01 00 88 2c d4 3f 50 79 01 00 de c0 ad 0b
74 03 00 eb 00 00 0f e1 1f 00 c0 e3 d3 00 80 e3
00 f0 29 e1 10 0f 11 ee 02 0a c0 e3 10 0f 01 ee
68 00 9f e5 10 0f 0c ee 09 00 00 eb 16 00 00 eb
ea 03 00 eb 11 0f 07 ee 9a 0f 07 ee 95 0f 07 ee
48 00 9f e5 09 00 80 e0 10 0f 0c ee 1e ff 2f e1
1e ff 2f e1 00 00 a0 e3 13 0f 08 ee 15 0f 07 ee
d5 0f 07 ee 9a 0f 07 ee 95 0f 07 ee 10 0f 11 ea
02 0a c0 e3 07 00 c0 e3 02 00 80 e3 02 0b 80 e3
01 0a 80 e3 10 0f 01 ee 0e f0 a0 e1 08 03 00 ea
00 04 2f 40 00 f0 20 e3 80 30 9f e5 30 40 2d e9
00 20 93 e1 88 10 92 e5 00 20 93 e1 2c 40 92 e5
00 20 93 e1 a8 c0 92 e5 00 20 93 e1 04 50 a0 e3
88 50 82 e5 00 50 93 e1 50 20 9f e5 20 50 95 e5
01 08 55 e3 fa ff ff 1a a4 39 a0 e1 83 39 a0 e1
17 30 83 e3 00 34 83 e1 00 40 92 e1 1f 00 c0 e1
01 00 80 e3 2c 30 84 e5 00 30 92 e1 07 10 81 e3
a8 00 83 e1 00 30 92 e5 88 10 83 e1 00 30 92 e5
20 30 93 e1 01 00 53 e3 fb ff ff 1a 30 80 bd e8
d8 7d 30 40 1c 31 9f e5 f0 40 2d e9 00 20 93 e1
90 20 92 e5 00 10 93 e1 68 50 91 e5 00 10 93 e1
80 40 91 e5 00 10 93 e1 84 c0 91 e5 00 10 93 e1
d8 10 91 e5 00 60 93 e1 04 70 a0 e3 90 70 86 e5
03 70 a0 e1 00 60 97 e5 d8 30 9f e5 5c 60 96 e5
01 08 56 e3 fa ff ff 1a 32 00 50 e3 a5 01 a0 e1
80 09 a0 e1 17 00 00 1a 32 00 80 e3 17 00 80 e3
00 50 93 e1 1f 40 c4 e3 01 40 84 e3 68 00 85 e5
00 00 93 e1 1f c0 cc e3 01 c0 8c e3 80 40 80 e5
00 00 93 e1 1f 10 c1 e3 01 10 81 e3 84 c0 80 e5
00 00 93 e1 07 20 82 e3 d8 10 80 e5 00 10 93 e1
90 20 81 e5 00 20 93 e1 5c 20 92 e5 01 00 52 e3
fb ff ff 1a f0 80 bd e8 fa 0b 80 e3 17 00 80 e3
00 50 93 e1 1f 40 c4 e3 0a 40 84 e3 68 00 85 e5
00 00 93 e1 1f c0 cc e3 08 c0 8c e3 80 40 80 e5
00 00 93 e1 1f 10 c0 e3 04 10 81 e3 84 c0 80 e5
00 00 93 e1 07 20 82 e3 d8 10 80 e5 00 10 93 e1
90 20 81 e5 00 20 93 e1 5c 20 92 e5 01 00 52 e3
fb ff ff 1a f0 80 bd e8 d8 7d 30 40 84 30 9f e5
30 40 2d e9 00 20 93 e1 94 10 92 e5 00 20 93 e1
40 40 92 e5 00 20 93 e1 a0 c0 92 e5 07 10 c1 e3
04 50 81 e3 00 20 93 e1 94 50 82 e5 00 50 93 e1
50 20 9f e5 34 50 95 e5 01 08 15 e3 fa ff ff 0a
a4 39 a0 e1 83 39 a0 e1 17 30 83 e3 00 34 83 e1
00 40 92 e1 1f 00 cc e3 01 00 80 e3 40 30 84 e5
00 30 92 e1 07 10 81 e3 a0 00 83 e1 00 30 92 e5
94 10 83 e1 00 30 92 e5 34 30 93 e1 01 00 13 e3
fb ff ff 0a 30 80 bd e8 d8 7d 30 40 24 30 9f e5
02 20 a0 e3 00 10 93 e1 d0 20 81 e5 00 10 93 e1
28 20 81 e5 00 20 93 e1 28 20 92 e1 02 00 52 e3
fb ff ff 1a 1e ff 2f e1 dc 7d 30 40 10 40 2d e9
4b 0f a0 e3 5f ff ff eb 32 00 a0 e3 80 ff ff eb
5c 33 9f e5 00 20 93 e1 8c 10 92 e5 00 20 93 e1
9c c0 92 e5 00 20 93 e1 ac 00 92 e5 00 20 93 e1
04 40 a0 e3 8c 40 82 e5 00 40 93 e1 30 23 9f e5
70 40 94 e5 01 08 54 e3 fa ff ff 1a ac 39 a0 e1
83 39 a0 e1 0f 39 83 e3 17 30 83 e3 00 c0 92 e1
7f 00 c0 e3 05 00 80 e3 9c 30 8c e5 00 30 92 e1
07 10 81 e3 ac 00 83 e1 00 30 92 e5 8c 10 83 e1
00 30 92 e5 70 30 93 e1 01 00 53 e3 fb ff ff 1a
dc 32 9f e5 03 28 a0 e3 00 30 93 e1 7c 20 83 e1
d0 32 9f e5 02 10 a0 e3 00 20 93 e1 e0 10 82 e5
03 10 a0 e1 00 20 91 e5 b8 32 9f e5 e0 20 92 e5
02 00 52 e3 fa ff ff 1a 00 10 93 e1 60 20 81 e5
03 10 a0 e1 00 20 91 e5 60 20 92 e1 02 00 52 e3
90 32 9f e5 fa ff ff 1a 00 10 93 e1 64 20 81 e5
00 20 93 e1 64 20 92 e1 02 00 52 e3 fb ff ff 1a
6c 32 9f e5 00 10 93 e1 0c 20 81 e5 00 20 93 e1
0c 20 92 e5 02 00 52 e3 fb ff ff 1a 54 32 9f e5
00 10 93 e1 dc 20 81 e5 03 10 a0 e1 00 20 91 e5
40 32 9f e5 dc 20 92 e5 02 00 52 e3 fa ff ff 1a
00 10 93 e1 20 21 81 e5 00 20 93 e1 20 21 92 e5
02 00 52 e3 fb ff ff 1a 14 32 9f e5 00 10 93 e1
03 00 a0 e1 08 20 81 e5 00 20 90 e5 00 12 9f e5
08 30 92 e1 02 00 53 e3 fa ff ff 1a f4 21 9f e5
00 00 92 e1 0c 30 80 e5 00 00 92 e1 00 30 80 e5
00 00 91 e5 00 30 80 e5 00 00 92 e1 08 30 80 e5
00 00 92 e1 04 30 80 e5 00 00 91 e5 04 30 80 e5
00 30 91 e5 04 30 93 e1 02 00 53 e3 fb ff ff 1a
b0 11 9f e5 00 20 92 e1 80 30 82 e5 00 30 91 e5
80 20 93 e1 02 00 52 e3 fb ff ff 1a 98 31 9f e5
01 10 a0 e3 00 30 93 e1 08 10 83 e1 80 31 9f e5
00 10 93 e1 b4 20 81 e5 00 20 93 e1 b4 20 92 e5
02 00 52 e3 fb ff ff 1a 68 31 9f e5 00 10 93 e1
30 20 81 e5 03 10 a0 e1 00 20 91 e5 54 31 9f e5
30 20 92 e1 02 00 52 e3 fa ff ff 1a 00 10 93 e1
40 20 81 e5 03 10 a0 e1 00 20 91 e5 40 20 92 e1
02 00 52 e3 2c 31 9f e5 fa ff ff 1a 00 10 93 e1
3c 20 81 e5 00 20 93 e1 3c 20 92 e5 02 00 52 e3
fb ff ff 1a 08 31 9f e5 00 10 93 e1 b8 20 81 e5
00 20 93 e1 b8 20 92 e5 02 00 52 e3 fb ff ff 1a
f0 30 9f e5 00 10 93 e1 ac 20 81 e5 03 10 a0 e1
OOB:
ff ff c8 b0 e8 12 b2 4a
63 70 83 0f c6 76 57 00
97 44 d0 70 e4 83 88 03
da d2 0b ae bc 00 12 39
d2 12 c2 02 57 a1 69 b0
81 29 45 00 5a 42 b2 08
68 5e c1 f0 18 98 cb 5a
9a 00 ff ff ff ff ff ff

0 John Murphy1 over 11 years ago in reply to Gary Wu

Expert 1210 points

It looks like the first sector (512 bytes of data) and first ECC (14 bytes of oob after 0xff 0xff) are identical, which is good.

0 Gary Wu over 11 years ago in reply to John Murphy1

TI__Expert 3313 points

Coud you share the images can run on GPEVM? I could test them on my GPEVM.

I am not sure if the issue is due to NAND version.

My GPEVM is a old one with 8 bit NAND flash.

0 John Murphy1 over 11 years ago in reply to Gary Wu

Expert 1210 points

I can't help you with that.

Our design was actually designed to run on custom hardware (based on the BeagleBone, but with 16-bit NAND).

During early development, I did try using the GPEVM (which is 8-bit NAND, and has a rather weird big CPLD doing some heavy magic pin mux'ing). I can't remember any specific problems with 8-bit NAND on the GPEVM though, after all, u-boot works with NAND out of the box. Just make sure you set the SYSBOOT pin switches appropriately.

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