Customer's I2C Question

Also, did you see this on the Wiki: http://processors.wiki.ti.com/index.php/I2C_Tips  ?

A common mistake is to neglect checking for a NACK.  When everything is working properly there is no problem.  However, checking for a NACK and handling it can save you lots of time.  For example, if you have a board with a hardware problem then the NACK detection can quickly help you identify those issues.  If you are operating the I2C through polling, you simply need to change your polling such that you poll XRDY/RRDY as well as ARDY.

Hi Biser,

Sorry, forgot to include: AM389x.

Best Regards,

Wallace

Unfortunately, this did not answer the customer question. Thank you though.I'm walking the customer through the TRM. He is using polling method. We are getting close but still need some guidance. Thanks for your assistance so far.  

xWallace

Hi Wallace,

What about the status of RRDY_IE (Bit 3 field) of I2C_IRQENABLE_CLR Register?

If Receive ready interrupt enable (RRDY_IE) bit is set, we shall confirm I2C_DATA register contains the second byte and it is ready to read from. In case, eventhough this bit is set ( indicates, it is ready to read from), but still uP is attempting to read the same byte twice insted of second byte from I2C_DATA register, data is not cleared after the first read and obviously, read access will return to the previous read data value as specified in the AM389x Sitara ARM processor TRM.

http://www.ti.com/lit/sprugx7

Thanks & regards,

Sivaraj K

Hi Sivaraj,

The customer has come back with the following that they were able to get the system working. However there is some issues with the RRDY flag. Please help/advise:

"

All is working okay except I cannot clear the RRDY flag once it is set.

I am invoking multiple calls to the driver and the first call is fine, it polls on (RRDY == 1), but when I try to clear RRDY for future transactions, it won't clear.

My understanding of how RRDY works is as follows:

• RRDY flag is set when the contents of RX FIFO buffer >= FIFO THRSH
• RRDY flag is cleared by writing a 1 to the RRDY bit in I2C_IRQSTATUS_RAW
• RRDY flag will be re-asserted if the contents of RX FIFO buffer >= FIFO THRSH

So, RRDY *should* be cleared with the following sequence:

1. RX THRSH = 2 (I2C_BUF |= (1 << 8))

1. Read both bytes

1. Just in case, I clear Tx and Rx FIFOs (I2C_BUF) |= 0x4040)

1. Clear flag (I2C_IRQSTATUS_RAW &= I2C_IRQSTATUS_RAW_RRDY)

1. Note that I2C_BUFSTAT = 0x8002, so the RX FIFO is empty, therefore RRDY should not be re-asserted (unless I am mistaken)

So, what am I doing wrong, here?  Why can I not clear the RRDY flag?


"

Hi Wallace,

Thanks for your post.

We shall try clearing the RRDY through FIFO interrupt mode. Like, generating the RRDY interrrupt request to CPU, and the CPU detects the interrupt and it can be programmed to write/read the amount of data bytes specified by the corresponding FIFO threshold. Here the interrupt condition shall be cleared and the next interrupt can be asserted again when the RRDY condition is met again.

Alternatively, you shall try FIFO polling mode operation too, in this mode, I2C_IRQENABLE_SET.RRDY_IE will be disabled and the status of the module can be checking by polling the RRDY status registers (I2C_IRQSTATUS_RAW). The RRDY flag will accurately reflect the interrupt conditions mentioned in the FIFO interrupt mode.

For more details on the above, please refer Sections 11.2.13.1 & 11.2.13.2 in the AM389x Sitara TRM as below:

http://www.ti.com/lit/sprugx7

Thanks & regards,

Sivaraj K