I can use GPMC to write any data to FPGA, but I just could read 0 from FPGA under CE.
The same operation in starterware is OK.
Please help me to clarifiy the problem.
Here is my setting in wince:
void GPMCPinMuxSetup(void)
{
/* GPMC_AD0 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(0), 0x30);
/* GPMC_AD1 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(1), 0x30);
/* GPMC_AD2 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(2), 0x30);
/* GPMC_AD3 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(3), 0x30);
/* GPMC_AD4 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(4), 0x30);
/* GPMC_AD5 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(5), 0x30);
/* GPMC_AD6 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(6), 0x30);
/* GPMC_AD7 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(7), 0x30);
/* GPMC_AD8 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(8), 0x30);
/* GPMC_AD9 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(9), 0x30);
/* GPMC_AD10 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(10), 0x30);
/* GPMC_AD11 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(11), 0x30);
/* GPMC_AD12 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(12), 0x30);
/* GPMC_AD13 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(13), 0x30);
/* GPMC_AD14 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(14), 0x30);
/* GPMC_AD15 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_AD(15), 0x30);
/* GPMC_WAIT0 */
OUTREG32( g_CTL_base + CONTROL_CONF_GPMC_WAIT0,
( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT));
/* GPMC_WPN */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_WPN,
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT));
/* GPMC_CS0 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_CSN(0), 0x00);
/* GPMC_CS1 */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_CSN(1), 0x00);
/* GPMC_ALE */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_ADVN_ALE, 0x00);
/* GPMC_BE0N_CLE */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_BE0N_CLE,
( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT ) |
( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT ) |
( 1 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT));
/* GPMC_OEN_REN */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_OEN_REN, 0x00);
/* GPMC_WEN */
OUTREG32(g_CTL_base + CONTROL_CONF_GPMC_WEN, 0x00);
}
void GPMCClkConfig(void)
{
SETREG32(g_PRCM_base + CM_PER_L3S_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
while((INREG32(g_PRCM_base + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
SETREG32(g_PRCM_base + CM_PER_L3_CLKSTCTRL, CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
while((INREG32(g_PRCM_base + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
SETREG32(g_PRCM_base + CM_PER_L3_INSTR_CLKCTRL, CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);
while((INREG32(g_PRCM_base + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) != CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);
SETREG32(g_PRCM_base + CM_PER_L3_CLKCTRL, CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);
while((INREG32(g_PRCM_base + CM_PER_L3_CLKCTRL) &
CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);
SETREG32(g_PRCM_base + CM_PER_OCPWP_L3_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
while((INREG32(g_PRCM_base + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
SETREG32(g_PRCM_base + CM_PER_GPMC_CLKCTRL, CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE);
while((INREG32(g_PRCM_base + CM_PER_GPMC_CLKCTRL) &
CM_PER_GPMC_CLKCTRL_MODULEMODE) != CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE);
SETREG32(g_PRCM_base + CM_PER_ELM_CLKCTRL, CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE);
while((INREG32(g_PRCM_base + CM_PER_ELM_CLKCTRL) &
CM_PER_ELM_CLKCTRL_MODULEMODE) != CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE);
while(!(INREG32(g_PRCM_base + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));
while(!(INREG32(g_PRCM_base + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));
}
void GPMC_Init(void)
{
//# Disable CS
OUTREG32(g_GPMC_base + GPMC_CONFIG7(0), 0x00000000);
OUTREG32(g_GPMC_base + GPMC_CONFIG7(1), 0x00000000);
//WAITPINSELECT Bit16
//DeviceSize 16Bit => Bit12
//MuxAddData Bit9
OUTREG32(g_GPMC_base + GPMC_CONFIG1(0), (1 << 16) + (1 << 12) + (1 << 9));
OUTREG32(g_GPMC_base + GPMC_CONFIG1(1), (1 << 16) + (1 << 12) + (1 << 9));
//CSONTME=0
//CSWROFFTIME= 30 = 0x1E => Bit16
//CSRDOFFTIME= 30 = 0x1E => Bit8
OUTREG32(g_GPMC_base + GPMC_CONFIG2(0), (0x1E << 16) + (0x1E << 8));
OUTREG32(g_GPMC_base + GPMC_CONFIG2(1), (0x1E << 16) + (0x1E << 8));
//ADVONTIME = 4 = 0x04 => Bit0
//ADVWROFFTIME = 10 = 0x0A => Bit16
//ADVRDOFFTIME = 10 = 0x0A => Bit8
OUTREG32(g_GPMC_base + GPMC_CONFIG3(0), (0x0A << 16) + (0x0A << 8) + (0x04 << 0));
OUTREG32(g_GPMC_base + GPMC_CONFIG3(1), (0x0A << 16) + (0x0A << 8) + (0x04 << 0));
//WEONTIME = 14 = 0x0E => Bit16
//WEOFFTIME = 20 = 0x14 => Bit24
//OEONTIME = 14 = 0x0E => Bit0
//OEOFFTIME = 30 = 0x1E => Bit8
OUTREG32(g_GPMC_base + GPMC_CONFIG4(0), (0x14 << 24) + (0x0E << 16) + (0x1E << 8) + (0x0E << 0));
OUTREG32(g_GPMC_base + GPMC_CONFIG4(1), (0x14 << 24) + (0x0E << 16) + (0x1E << 8) + (0x0E << 0));
//RDCycleTime = 30 = 0x1E => Bit0
//WRCycleTime = 30 = 0x1E => Bit8
//RDACCESSTIME = 2 = 0x00 => Bit16
//HWREG(0x50000070) = 0x000f1f1f;
OUTREG32(g_GPMC_base + GPMC_CONFIG5(0), (0x01 << 16) + (0x1E << 8) + (0x1E << 0));
OUTREG32(g_GPMC_base + GPMC_CONFIG5(1), (0x01 << 16) + (0x1E << 8) + (0x1E << 0));
//WRACCESSTIME = 0 = 0x00 => Bit24
//WRDATAONADMUXBUS = 10 = 0x0A => Bit16
//HWREG(0x50000074) = 0x000B0000;
OUTREG32(g_GPMC_base + GPMC_CONFIG6(0), (0x00 << 24) + (0x0A << 16));
OUTREG32(g_GPMC_base + GPMC_CONFIG6(1), (0x00 << 24) + (0x0A << 16));
//HWREG(0x50000078) = 0x00000f41;
//A24 = 1
//start address = 0x01000000
OUTREG32(g_GPMC_base + GPMC_CONFIG7(0), 0x00000F41);
//A25 = 1
//start address= 0x02000000
OUTREG32(g_GPMC_base + GPMC_CONFIG7(1), 0x00000F42);
}