66AK2H6 EVM, performance and change from Keystone 1 to Keystone 2

Tobias,

I'll try to address as many of these as possible, but they're from various areas and I will need to pull in the right people to address all the questions you've asked.

• Do you know when the EVMK2HX comes available in Europe?

I'll have to have someone from the marketing team get back to you on this.

• How easy is it to switch from the C667x to the 66AK2H6 in terms of software reusability?

This is should be relatively painless.  The MCSDK is written for re-usability across platforms.  There will be some changes but for the most parts the API's should remain the same.

• Are all the libraries/ interfaces (e.g. Hyperlink, IPC, DSPLib, Multicore programming..) of the SYS/BIOS and LINUX-MCSDK for both platforms the same? Which are the points we have to be aware of in our development? I have seen that the MCSDK 03_00_00_11 only supports the new Keystone II platforms for example.

I'll let someone from the SW team address this.

• So far I understand that the Keystone II architecture is pretty similar to the Keystone I, but increases the data backbone performance between the cores significantly. And it adds ARM cores as well as more I/O capabilities. Is there something else we have to be aware of, when changing platforms?

They are designed as an evolving architecture, and shouldn't have anything that would be a major surprise in terms of change in direction.  I don't think there's anything major to point out.

• Is there already a throughput performance guide like for the C66x Keystone I devices available? Can I assume that the Keystone II devices reach at least the Keystone I numbers?

We don't have one available as of yet, but you can expect to at least achieve the same performance levels for the same IPs.

• Is there data available for the performance of a FFT with 2048 points on a single C66x K2 DSP core (not the FFTC!)? We are interested in the calculation time.

I'll need input form the SW team.

• We are also interested in using the TCI6636K2H instead. As information about this SoC is pretty rare, can you provide us a release date for this chip? It has really nice Coprocessors.

The TCI66xx devices are only supported for specific projects, and also are not supported on the E2E forums.  You would need to work through your local Field Application Engineer, but you'll also probably want to discuss the availability of the TCI66xx devices with your local technical sales representative.

• Is there any data available for a 25 Gbit/s HyperLink throughput performance between a TMDXEVM6678L and a Xilinx Kintex-7 FPGA with the Integretek IP-HyperLink with a 0,5m HyperLink connection cable? Is it possible to reach the 15 Gbit/s in both directions?

I'll need to get someone else to address this.

Best Regards,

Chad

For Q7.

7. Is there any data available for a 25 Gbit/s HyperLink throughput performance between a TMDXEVM6678L and a Xilinx Kintex-7 FPGA with the Integretek IP-HyperLink with a 0,5m HyperLink connection cable? Is it possible to reach the 15 Gbit/s in both directions?

Their trace length is too long (0.5 meter) Hyperlink can show max throughput when the trace is less than 4 inches. We cannot guarantee that they can get 25 Gbps in that case and we don’t have any test result for such a harsh case.

When we tested Kepler VDB to VDB throughput with 30 inches trace without additional signal amplification, it was hard to make even PLL lock and link enable, because the side band signal was too weak and couldn’t finish the correct SERDES initial data training.  

Regards, Eric

1) Regarding EVMK2H, these should be orderable via estore.ti.com by early August.

5) 2k Single Precision complex-to-complex FFT is right around 14.2K cycles, real-to-complex will be slightly less

Regards,

Travis