FPGA to C6678 DSP interface

was thinking of using the dual port block RAM of SPARTAN6 (XC6SLX45T) to store all the blocks then interrupt the DSP (similar to the old design), but do I have to use the C6678 EMIF in this case? and is that a good idea?

Normally, I'd be suggesting SRIO, PCIe or SGMII.  Not sure of the major issue regarding the sequential transfer / interrupt.  You should be able to do it with SRIO and PCIe w/ interrupts.

That said, EMIF16 would be your next best bet assuming that it meets your throughput requirements.  

That said, what are you throughput requirements?

Best Regards,

Chad

Thank you Chad for your reply.

Background: Our current single channel system has a DDC that runs at 1.25 Msps. We perform over the air diagnostics and Time of Arrival (TOA) on narrow band public safety radios. a packet is about 10 blocks (10*3072*2 (I,Q) ). demodulating the packet is fast, but once a packet is detected, we need a lot of processing power to perform TOA calculations. this is done by a SWI and possible because we have 10 block time before the next packet is detected.

1- New design needs to perform the above calculations on 8 different channels, Each channel will be sampled at max 2 Mbps. Each core will have a different DSP load (different protocols, different channel). Each core need to be able to access any of the channel's output samples.

2- if we interrupt the DSP everytime a DDC is done sampling, will the overhead of the Interrupt/etc affect the performance/time constrains of the system?

3- keeping the process as a block-based will make migration from current system to multicore system easier! (?)

4-- Do you mind explain to me (big picture) the transfer path the samples need to take from the (PCIe, SRIO, etc) to the multi-core in order for all cores to access them.

Regards,

Murad

I'm not sure the Max 2 Mbps per channel matches with what you said of 1.25Msps (I,Q) data.  Assuming the I,Q data is 8bit data that's 20Mbps / Channel or 160Mbps total for 8 Channels.

This is more than you're estimate of 2Mbps / Chan. (or 16Mbps total) but easily within the reach of EMIF16 which is > 100MB/s.

Best Regards,

Chad

Sorry, I meant 1.25 Msps (max 2 Msps)...so, at 2 Msps: 2 Msps x 16 bis/sample x 2 (I,Q) * 16 channels (8 channels for now but may use diversity) = almost 1 Gbps

So to confirm:

- 16 bit data samples

- I,Q data

- 2Msps

- 8 Channels today but could grow to 16 channels. 

Giving a max of 1Gbps (or 125MB/s)

I went back and checked, and the theoretical limits of EMIF16 are going to be topping out closer to 300Mbps and would not be able to support this.

I'd say SRIO or PCIe, and using QMSS (Queue Management Subsystem) to direct the data to the appropriate cores and to alert the cores when the "packet" arrives. For clarification in this case Packet is referring to your Radio Packet and not SRIO or PCIe packet.

If more details are needed on this, it may be best to post a new question specifically about how to do that, and I'll direct it to the correct individuals to address, and that way they're not rehashing our discussion from above.

Best Regards,
Chad