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FPGA to C6678 shared memory

I need to transfer 16-channel (I,Q) samples each at 2 Msps/16-bit each = around 1 GBPS from Spartan6 toC6678 such that each core can access the data. I want to use PCIe and I like to interrupts the cores at block (3072 I, 3072 Q) bases if possible. read about QMSS but seems that it doesn't interface with PCIe. How to do this?. can one core receive the data and put it in MSMS so other cores can access it?

please refer to for more details:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/273529/955951.aspx#955951

 

Regards,

 

Murad

  • Murad,

    Not sure I followed your math, but assuming you are looking for 1 Gbps (B usually means Bytes), then the PCIe should work perfectly for you.

    The PCIe peripheral is a bus master in the C6678. This means it can read or write directly from or to the memory components of a C6678 system. In particular, you can look in the Data Manual (rev C) on page 92 Figure 4-2 to see the topology diagram and on page 93 Table 4-1 to see the Connections Matrix. The topology shows PCIe on the left side where all the masters drive onto the Teranet, and the Connections Matrix shows that the PCIe can access the MSMC_SES (DDR3), MSMC_SMS (MSMCSRAM), and all the CorePacs' SDMA buses for access to their internal L2 SRAM.

    Please refer to the PCIe section in the Data Manual for some specific details, and the PCIe User Guide for a complete understanding of the capabilities of this powerful peripheral.

    Regards,
    RandyP

  • Thank you Randy for your reply.

     

    I G bit/sec is my requirement.

    2 questions:

    1- Do we need a dedicated core to handle the PCIe TX/RX between the FPGA and the different cores?

    2- Does the FPGA need to sends the (I,Q) data sequentially to DSP or can I store the Data in FPGA DPRAM and use PCIe to transfer all data once we collected the correct amount?

     

    Regards,

     

    Murad

  • Murad,

    1 - You need 0 cores to handle the PCIe Tx/Rx data. The FPGA's PCIe can write directly to the C6678's DDR3 or MSMCSRAM. I tried to explain this in my previous post in the part about the PCIe being a bus master. You may want to review the PCIe User Guide to understand how it works.

    2 - The FPGA can send data however you want to send the data. If you want to store the data in a memory accessible through the FPGA, then the DSP can go get the data when the FPGA signals that it is ready. This can be automated using PKTDMA or EDMA3 servicing the PCIe to cause this transfer, or the FPGA can send data in bursts as it gets ready with data to send.

    You may want to go to TI.com and search for Keystone Training. There is a lot to understand about this family of devices, a lot of capability that you can learn about fairly easily by watching some videos.

    Regards,
    RandyP

  • Thank you Randy,

     

    Regards,

     

    Murad