Hi, everyone,
When i used the cache of C6678, there is problem.
In my program, I use several cores,
in the master core, i do as follow:
Cache_wb(data_ptr, , , );
MessageQ_put();
in the slave core, i do as follow:
MessageQ_get();
Cache_inv(data_ptr, ....);
But in the slave core, the data at the address 'data_ptr' sometimes is true, while sometimes is wrong.
In the SPRZ334D, C6678 Silicon Revision 1.0, 2.0 Silicon Errata, there is a Errata, 'Advisory 22 L2 Cache Corruption During Block and Global Coherence Operations
Issue', and there is a sentence,'This workaround requires that the memory system be idle during the block and global coherence operations',
Does it mean if i use Cache_inv() or other Cache functions, memory system must be idle? If there is a dma(for example, srio) acessing the ddr, this is not permitted?
If it is, how to solve the problem(There is a dma(for example, srio) acessing the ddr while i am using the cache functions.)?
qbliu,
thanks
